TI中文支持网在PWM_PSFB_VMC_SR_Cnf.c中epwm1和epwm2的同步输出选择为什么不一样？这样做有什么考虑吗？
(*ePWM[n]).TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
(*ePWM[n]).TBPRD = period;
(*ePWM[n]).CMPA.half.CMPA = period/2; // Fix duty at 50%
(*ePWM[n]).TBPHS.half.TBPHS = 0;
(*ePWM[n]).TBCTR = 0;
(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
(*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //used to sync EPWM(n+1) "down-stream"
(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;
(*ePWM[n]).AQCTLA.bit.ZRO = AQ_SET;
(*ePWM[n]).AQCTLA.bit.CAU = AQ_CLEAR;
(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
(*ePWM[n]).DBRED = 20; // dummy value for now
(*ePWM[n]).DBFED = 20; // dummy value for now
// ePWM(n+1) init. EPWM(n+1) is a slave
(*ePWM[n+1]).TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
(*ePWM[n+1]).TBPRD = (period-1);
(*ePWM[n+1]).CMPA.half.CMPA = period/2; // Fix duty at 50%
(*ePWM[n+1]).TBPHS.half.TBPHS = 0; // zero phase initially
(*ePWM[n+1]).TBCTR = 0;
(*ePWM[n+1]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
(*ePWM[n+1]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync "flow through" mode
(*ePWM[n+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n+1]).TBCTL.bit.CLKDIV = TB_DIV1;
bad：
(*ePWM[n+2]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass the Sync signal through to (*ePWM[n+3])
跟同步整流相关？
在PWM_PSFB_VMC_SR_Cnf.c中epwm1和epwm2的同步输出选择为什么不一样？这样做有什么考虑吗？
(*ePWM[n]).TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
(*ePWM[n]).TBPRD = period;
(*ePWM[n]).CMPA.half.CMPA = period/2; // Fix duty at 50%
(*ePWM[n]).TBPHS.half.TBPHS = 0;
(*ePWM[n]).TBCTR = 0;
(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
(*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //used to sync EPWM(n+1) "down-stream"
(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;
(*ePWM[n]).AQCTLA.bit.ZRO = AQ_SET;
(*ePWM[n]).AQCTLA.bit.CAU = AQ_CLEAR;
(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
(*ePWM[n]).DBRED = 20; // dummy value for now
(*ePWM[n]).DBFED = 20; // dummy value for now
// ePWM(n+1) init. EPWM(n+1) is a slave
(*ePWM[n+1]).TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
(*ePWM[n+1]).TBPRD = (period-1);
(*ePWM[n+1]).CMPA.half.CMPA = period/2; // Fix duty at 50%
(*ePWM[n+1]).TBPHS.half.TBPHS = 0; // zero phase initially
(*ePWM[n+1]).TBCTR = 0;
(*ePWM[n+1]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
(*ePWM[n+1]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n+1]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync "flow through" mode
(*ePWM[n+1]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n+1]).TBCTL.bit.CLKDIV = TB_DIV1;
囧：
回复 bad:
PWM1和PWW2控制的是原边管子，PWM1是master，PWM2是SLAVE，因为是相移全桥，所以控制原理是通过原边的对管之间的相移来调整输出特性，PWM3是SR，SR是要跟着原边管子开关的，所以也要与原边管子同步
