TI中文支持网TI工程师：
您好！最近看了《Three-Phase High PWM Frequency GaN Inverter Reference Design TIDA-00915》参考设计。对里面的高速电路有一些细节不理解，请指点。
电路信号链路如下图所示。tms320f28377d的PWM作为时钟信号通过 buffer（CDCLVC1102PW）为4片Sigma-Delta ADC转换器（图中只画了2片）提供时钟信号。设计者考虑阻抗匹配，并联两个100欧姆和串联22欧姆电阻实现阻抗匹配。但为什么会串入0.1uF的电容呢？
具体问题如下：
1、将Sigma-Delta ADC输出信号串入0.1uF电容，再进入DSP管脚，是阻抗匹配的需要吗？串入容值的大小计算，您能推荐文档吗？
2、设计者也不是所有都串入了0.1uF电容，直流母线电压测量的clk，就没有串入。是漏掉了，还是其它原因呢？
3、设计者多处串入0欧姆电阻，是调试需要，（因为28377的Sigma-Delta ADC模式2 可以不需要时钟信号），还是有其它讲究？
4、关于何时需要考虑阻抗匹配？一些文档说，对于20MHz信号，PCB走线超过50mm，就需要考虑。另一文献说信号上升沿和下降沿小于6倍信号延时就需要考虑。您对何时需要考虑，有什么建议吗？因为TI参考电路《使用 SAR 和 Σ-Δ ADC 在保护继电器中实现集成诊断功能的参考设计 TIDA-00810》同样的电路，就没有考虑阻抗匹配。
Kailyn Chen：
这篇应用手册没有细读过，但是图中的0.1uF 是AC耦合电容 。 耦合电容的取值大小在于信号频率，通常0.1uF，0.22uF是经验值，适合频率不太高的应用。如果在高速应用中，0.1uF就不起作用了。
至于零欧姆电阻作用，通常我们在ADC中看到当模拟地和数字地分开时，通过0ohm电阻实现单点接地，减小回流路径，其次可以当跳线用，方便调试。
阻抗匹配的话，一般低频的时候可以不用考虑。当高频，或者传输线比较长的时候，防止信号反射，考虑信号完整性，一般会考虑阻抗匹配，或者一些特殊应用，比如视频，通常考虑75ohm阻抗匹配。
huichen：
回复 Kailyn Chen:
感谢您的回复。时钟信号是20MHz，您提到的“频率不太高的应用”，是指多少MHz呢？串入上AC耦合电容，相对于不串入有什么好处呢？因为不加，这个串行信号读取也是没有问题的，因为TI得很多案例，都是没有串入这个AC电容的，我们正在调试正常运行的电路也没有串入这个AC电容。
huichen：
回复 Kailyn Chen:
还有一个问题，就是cdclvc1102可以驱动多少个芯片？是cdclvc1102最大输出电流能力确定的吗？AMC1306 datasheet上clk输入管脚耗电量不明确，cdclvc1102最大输出电流50mA，但没有关于输出电流与输出电压幅值的关系图。
Seasat Liu：
回复 huichen:
耦合分为交流耦合和直流耦合
原理图上是交流耦合
你用的是直流耦合
各有各的优缺点
huichen：
Hello ,
looks like this a modified schematic from the Altium design files. Please see the variants information in Altium, which show that some resistors are DNP.
(1) I had the 0.1uF capacitor on the data signal, it does not have an effect in the impedance matching of the data signal. The 0.1uF capacitor would be low impedance to the 20Mhz data signal. This was kept for testing. Please remove this capacitor and replace with a short. Thanks, I will add a note in design guide to make it clear.
(2) Some resistors are for debugging.
R12 and R16 on clock lines are DNP when using the Manchester encoded version of AMC1306 as there is no need to give the clock back to C2000 when data is Manchester encoded.
R4, R7, R15 and R17 are used for debugging either open or short according to the need. This can be eliminated.
R5, R13, R3,R6 are for impedance matching (series termination).
Also, R1 and R8, or R11 and R14 are placed for parallel termination, this should not be placed when using series termination. After testing i have seen that series termination works best.
(3) I had long distance and also a cable between AMC1306 and C2000 about 10cm. The issues due to propagation delay is eliminated by using Manchester encoded data. However impedance matching is required for signal integrity. Example: one of the problems I have seen with out impedance matching is excessive ringing at the signal edges. I have done only a rough impedance matching using the resistors, but I have not done the impedance control in the PCB manufacturing. At 20Mhz one may not see a problem depending on the board and cable, I would still put it as provision.
also note, CDCLVC1102 has a internal series termination resistance for 50Ohm. You may need to add to this.
(4) TIDA-00915-C does have provision for 4 clock input to the C2000, but since I am using the Manchester version of the AMC1306, I have DNP resistors on these clock lines. effectively I have only 4 AMC1306, being driven. This works very well for TIDA-00915, unfortunately, I do not have any info on the max number of AMC1306. Please do post on the Clock and Timing Forum about max number of loads for CDCLVC1102.
Regards
Nelson
huichen：
回复 huichen:
现在就剩下最后一个问题了，如何评估CDCLVC1102的驱动能力。
