TI中文支持网芯片手册关于uPP接口的DMA重载transfer descriptors的叙述比较简短：
Each DMA channel allows a second descriptor to be queued while the previously programmed DMA
transfer is still running. The UPxS2.PEND bit reports whether a new set of DMA parameters may be
written to the DMA descriptor registers. Each DMA channel can have at most one active transfer and one
queued transfer. This allows each I/O channel to perform uninterrupted, consecutive transactions across
DMA transfer boundaries.
The internal DMA controller does not support automatically reloading DMA transfer descriptors. Each
successive descriptor set must be explicitly written to the UPxDn registers by software
该段说DMA控制器不支持自动重载transfer descriptors，需要手动修改UPxDn registers。问题是，手动修改UPxDn registers会影响正在运行的DMA传输吗？正确的修改操作过程是怎样的？怎么保证在当前传输结束前及时修改transfer descriptors。
Tony Tang：
Each DMA channel allows a second descriptor to be queued while the previously programmed DMAtransfer is still running. The UPxS2.PEND bit reports whether a new set of DMA parameters may bewritten to the DMA descriptor registers. Each DMA channel can have at most one active transfer and onequeued transfer. This allows each I/O channel to perform uninterrupted, consecutive transactions acrossDMA transfer boundaries.
发起一个后，检查UPxS2.PEND 位，如果为0，则可以写入下一个传输参数，前面的参数已经在被执行，新的参数只是放到队列里。在后面的中断里还是这么做，就达到了及时更新的目的，因为第一个中断是第一个配置的，这里第二个配置开始传输了，所以可以在中断里更新第三个配置了，以此类推。
