TI中文支持网6748中upp的UPICR中CLKINVA位，TI的手册上的描述是：
Channel A clock inversion. Controls clock signal polarity for interface Channel A.
0 Clock is not inverted. Channel A signals align on rising edge of clock.
1 Clock is inverted. Channel A signals align on falling edge of clock.
请问当CLKINVA 位为0 的时候， signal align on rising edge of clock. 指的是数据在传输是发生在时钟的上升沿？还是指的是这些upp有关的信号线是在上升沿的时候开始对齐？？？
请指导，谢谢！！
Tony Tang：
TRM手册：
33.2.5.6 CLOCK SignalThe uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals alignon the rising edge of CLOCK, but its polarity is controlled by the CLKINVx bit in UPICR. The activeedge(s) of CLOCK should always slightly precede transitions of other uPP signals.In transmit mode, CLOCK is an output signal; in receive mode, CLOCK is an input signal. SeeSection 33.2.1 for more information on clock generation and allowed frequencies.
