TI中文支持网我目前用TMDSPLCKIT-V3-C2000的PLC
然后在你们PLC本身的CC码在包上一层RS码
目前我RS码的长度有
code rate 0.25 ：(31,7,12) 、(63,15,24) 、(127,31,48)
code rate 0.5 ：(31,15,8)、(63,31,16)、(127,63,32)
code rate 0.75 ：(31,23,4)、(63,41,11)、(127,95,16)
但是当我RUN以下参数时，却一直跑到ILLEGAL_ISR这中断常式去
code rate 0.25 ：(63,15,24) 、(127,31,48)
code rate 0.5 ：(127,63,32)
code rate 0.75 ：(127,95,16)
我查了.cmd的memory长度大小都没有冲突到，且.map空间都写足够
我这到底是空间溢出还是怎样？我把.stack弄大看.map的stack也都没被我用光阿
附上我的F28069.cmd和F28069.map，我将RAMM0和M1合并起来了
/*
// TI File $Revision:
// Checkin $Date:
//###########################################################################
//
// FILE: F28068.cmd
//
// TITLE: Linker Command File For F28068 Device
//
//###########################################################################
// $TI Release:
// $Release Date:
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// —————————————
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\F2806x_headers\cmd
//
// For BIOS applications add: F2806x_Headers_BIOS.cmd
// For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// ————————————–
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28068 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHGF : origin = 0x3DC000, length = 0x008000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x008000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
/* RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ /*RAMM0 : origin = 0x000050, length = 0x0003B0 */
/* RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ /* RAMM1 : origin = 0x000400, length = 0x000400 */
RAMM0M1 : origin = 0x000050, length = 0x0007B0
RAML234 : origin = 0x008C00, length = 0x005400 /* on-chip RAM block L2 */
RAML5678 : origin = 0x00E000, length = 0x006000 /* on-chip RAM block L5 */
/*FLASHC : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
sys_entry : > 0x3dC000, PAGE = 0 /* crc */
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHC, PAGE = 0
codestart : > BEGIN, PAGE = 0
/*
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
*/
/* from csl */
ramfuncs : > FLASHD, PAGE = 0 /* Used by file CodeStartBranch.asm */
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0M1, PAGE = 1
.ebss : > RAML234, PAGE = 1
.esysmem : > RAML234, PAGE = 1
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHC, PAGE = 0
.switch : > FLASHC, PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
DMARAML5 : > RAML5678, PAGE = 1
DMARAML6 : > RAML5678, PAGE = 1
DMARAML7 : > RAML5678, PAGE = 1
DMARAML8 : > RAML5678, PAGE = 1
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
SECTIONS
{
CRC8_TABLE : > FLASHD, PAGE = 0 /* Can be Flash */
CRC16_TABLE : > FLASHD, PAGE = 0 /* Can be Flash */
CRC32_TABLE : > FLASHD, PAGE = 0 /* Can be Flash */
PHY_TABLE : > FLASHD, PAGE = 0 /* Can be Flash */
PHY_TABLE_TX : > RAML234, PAGE = 1 /* Can be Flash */
PHY_TABLE_RX : > RAML234, PAGE = 1 /* Can be Flash */
PHY_RESERVED_BUF : > RAML5678, PAGE = 1
PHY_DATA_BUF : > RAML5678, PAGE = 1
/* shadow memory for work buffers */
.shadow : > RAML5678, PAGE = 1 /* must be different from the main data memory */
/* Flash initialization must run from RAM */
secureRamFuncs : LOAD = FLASHD, PAGE = 0
RUN = RAML234, PAGE = 1
/*RUN = RAML5678, PAGE = 1*/
LOAD_START(_secureRamFuncs_loadstart),
LOAD_END(_secureRamFuncs_loadend),
RUN_START(_secureRamFuncs_runstart)
/* ISR from RAM */
isrRamFuncs : LOAD = FLASHD, PAGE = 0
RUN = RAML234, PAGE = 1
/*RUN = RAML5678, PAGE = 1*/
LOAD_START(_isrRamFuncs_loadstart),
LOAD_END(_isrRamFuncs_loadend),
RUN_START(_isrRamFuncs_runstart)
/* PHY functions that needs to be from RAM */
phyRamFuncs : LOAD = FLASHD, PAGE = 0
RUN = RAML234, PAGE = 1
/*RUN = RAML5678, PAGE = 1*/
LOAD_START(_phyRamFuncs_loadstart),
LOAD_END(_phyRamFuncs_loadend),
RUN_START(_phyRamFuncs_runstart)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Linda：
您好！
产生Illegal ISR非法中断的可能原因有：
(1)无效指令被解码（包括无效寻址模式）；
(2)操作码0000被解码，相当于ITRAP0指令；
(3)操作码FFFF被解码，相当于ITRAP1指令；
(4) 某个32位的操作尝试使用@SP寄存器寻址模式；
(5) 寻址模式设置为AMODE=1和PAGE0=1.
建议可以从以上几个方面寻找原因。
