TI中文支持网如下面的函式, 我設定2組PaRAM Set, 要使用link transfer傳輸byteCount大小的資料,
BIDX = 32640, 一組PaRAM傳輸32640的倍數資料, 另一組PaRAM傳輸小於32640剩餘的資料
第二組的TCC uiChannel2 = uiChannel+1; 這樣會有問題嗎?
能否幫我查看是那裡錯了, 謝謝
void Memcpy_DMA_Modify2(unsigned int dstAddress, unsigned int srcAddress, unsigned int byteCount)
{
CSL_TpccRegs* EDMACCRegs;
unsigned int uiChannel, uiChannel2, uiChannelShift, ACNTSize, uiBCNT, BIDX = 32640;//32512 32768
volatile Uint32 * TPCC_ESR;
volatile Uint32 * TPCC_IPR;
volatile Uint32 * TPCC_ICR;
EDMA_CC_Channel_Num CC_channel;
CC_channel = TC_channel_Table[0];
EDMACCRegs= gpEDMA_CC_regs[CC_channel>>16];
uiChannel = CC_channel&0xFF;
if(uiChannel<32)
{
TPCC_ESR= &EDMACCRegs->TPCC_ESR;
TPCC_IPR= &EDMACCRegs->TPCC_IPR;
TPCC_ICR= &EDMACCRegs->TPCC_ICR;
uiChannelShift= uiChannel;
}
else
{
TPCC_ESR= &EDMACCRegs->TPCC_ESRH;
TPCC_IPR= &EDMACCRegs->TPCC_IPRH;
TPCC_ICR= &EDMACCRegs->TPCC_ICRH;
uiChannelShift= uiChannel – 32;
}
ACNTSize = byteCount%BIDX;
if(ACNTSize != 0)
{
//second PaRAM
byteCount -= ACNTSize;
unsigned int srcAddress2 = srcAddress + ACNTSize;
unsigned int dstAddress2 = dstAddress + ACNTSize;
uiChannel2 = uiChannel+1;
uiBCNT = byteCount/BIDX;
if(uiBCNT>65535)
uiBCNT= 65535;
if(uiBCNT != 0)
{
EDMACCRegs->PARAMSET[uiChannel2].OPT=
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, //Intermediate transfer completion chaining
CSL_EDMA3_TCCH_DIS, //Transfer complete chaining
CSL_EDMA3_ITCINT_DIS, //Intermediate transfer completion interrupt
CSL_EDMA3_TCINT_EN, //Transfer complete interrupt
uiChannel2, //Transfer complete code(TCC): 6-bit code sets the relevant bit in the chaining enable register(CER) for chaining or in the interrupt pending register(IPR) for interrupts.
CSL_EDMA3_TCC_NORMAL, //TCC mode
CSL_EDMA3_FIFOWIDTH_NONE, //FIFO Width
CSL_EDMA3_STATIC_DIS, //keep PARAM uncharged
CSL_EDMA3_SYNC_A, //A synchronization
CSL_EDMA3_ADDRMODE_INCR, //Destination address mode //1
CSL_EDMA3_ADDRMODE_INCR); //Source address mode //1
EDMACCRegs->PARAMSET[uiChannel2].SRC= GLOBAL_ADDR(srcAddress2);
EDMACCRegs->PARAMSET[uiChannel2].SRC_DST_BIDX= CSL_EDMA3_BIDX_MAKE(BIDX, BIDX); //BIDX range from -32768 to 32767
EDMACCRegs->PARAMSET[uiChannel2].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF, 0); //0xFFFF is specified a null link
EDMACCRegs->PARAMSET[uiChannel2].SRC_DST_CIDX= CSL_EDMA3_CIDX_MAKE(0,0);
EDMACCRegs->PARAMSET[uiChannel2].CCNT= 1;
EDMACCRegs->PARAMSET[uiChannel2].A_B_CNT= CSL_EDMA3_CNT_MAKE(BIDX, uiBCNT); //BCNT is between 1 to 65535
EDMACCRegs->PARAMSET[uiChannel2].DST= GLOBAL_ADDR(dstAddress2);
}
unsigned int* linkPaRAM = (unsigned int *)&(EDMACCRegs->PARAMSET[uiChannel2]);
EDMACCRegs->PARAMSET[uiChannel].OPT=
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, //Intermediate transfer completion chaining
CSL_EDMA3_TCCH_DIS, //Transfer complete chaining
CSL_EDMA3_ITCINT_DIS, //Intermediate transfer completion interrupt
CSL_EDMA3_TCINT_EN, //Transfer complete interrupt
uiChannel, //Transfer complete code(TCC): 6-bit code sets the relevant bit in the chaining enable register(CER) for chaining or in the interrupt pending register(IPR) for interrupts.
CSL_EDMA3_TCC_NORMAL, //TCC mode
CSL_EDMA3_FIFOWIDTH_NONE, //FIFO Width
CSL_EDMA3_STATIC_DIS, //keep PARAM updated
CSL_EDMA3_SYNC_A, //AB synchronization
CSL_EDMA3_ADDRMODE_INCR, //Destination address mode //1
CSL_EDMA3_ADDRMODE_INCR); //Source address mode //1
EDMACCRegs->PARAMSET[uiChannel].SRC= GLOBAL_ADDR(srcAddress);
EDMACCRegs->PARAMSET[uiChannel].SRC_DST_BIDX= CSL_EDMA3_BIDX_MAKE(0, 0); //BIDX range from -32768 to 32767
EDMACCRegs->PARAMSET[uiChannel].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0x4020, 0); //0xFFFF is specified a null link
EDMACCRegs->PARAMSET[uiChannel].SRC_DST_CIDX= CSL_EDMA3_CIDX_MAKE(0,0);
EDMACCRegs->PARAMSET[uiChannel].CCNT= 1;
EDMACCRegs->PARAMSET[uiChannel].A_B_CNT= CSL_EDMA3_CNT_MAKE(ACNTSize, 1);
EDMACCRegs->PARAMSET[uiChannel].DST= GLOBAL_ADDR(dstAddress);
//Manually trigger the EDMA//
(*TPCC_ESR)= 1<<(uiChannelShift);
//wait for completion//
while(0==((*TPCC_IPR)&(1<<(uiChannelShift))));
//clear completion flag//
(*TPCC_ICR)= 1<<(uiChannelShift);
}
}
Chia-Hung Chen1：
第一組的uiChannel = 0, 第二組的uiChannel2 =uiChannel +1 = 1,
所以第二組的PaRAM SET位址是0x4020, 我link到0x4020, 我查看CC0 PaRAM SET初始位置是0x02704000, 每加1就多20
Chia-Hung Chen1：
回复 Chia-Hung Chen1:
我自己測出來了,下面那組的PaRAM SET,
CSL_EDMA3_TCCH_DIS要改成CSL_EDMA3_TCCH_EN就可以了,
和Ping-Pong寫的不一樣
Shine：
回复 Chia-Hung Chen1:
感谢分享解决方法。
Chia-Hung Chen1：
回复 Shine:
啊~抱歉, 我剛才測試, 兩組PaRAM SET都有傳輸, 但是第2組傳輸後的結果卻不正確, 看來還要再測試了
Chia-Hung Chen1：
我是使用DSP 6678, EVM板子, CCS版本5.4
如下面的函式, 我設定2組PaRAM Set, 要使用link transfer傳輸byteCount大小的資料,
BIDX = 32640, 第一組PaRAM(下面那組)傳輸小於32640剩餘的資料, 傳輸完會Link到上面那組PaRAM, 傳輸32640的倍數資料,
上面那組的TCC uiChannel2 = uiChannel+1;
能否幫我查看是那裡錯了, 它只會傳下面那組小於32640的資料, 不會傳上面那個PaRAM資料,
或是有Link傳輸的範例可以參考嗎? 謝謝
void Memcpy_DMA_Modify2(unsigned int dstAddress, unsigned int srcAddress, unsigned int byteCount){CSL_TpccRegs* EDMACCRegs;unsigned int uiChannel, uiChannel2, uiChannelShift, ACNTSize, uiBCNT, BIDX = 32640;//32512 32768volatile Uint32 * TPCC_ESR;volatile Uint32 * TPCC_IPR;volatile Uint32 * TPCC_ICR;EDMA_CC_Channel_Num CC_channel;
CC_channel = TC_channel_Table[0];
EDMACCRegs= gpEDMA_CC_regs[CC_channel>>16];uiChannel = CC_channel&0xFF;if(uiChannel<32){TPCC_ESR= &EDMACCRegs->TPCC_ESR;TPCC_IPR= &EDMACCRegs->TPCC_IPR;TPCC_ICR= &EDMACCRegs->TPCC_ICR;uiChannelShift= uiChannel;}else{TPCC_ESR= &EDMACCRegs->TPCC_ESRH;TPCC_IPR= &EDMACCRegs->TPCC_IPRH;TPCC_ICR= &EDMACCRegs->TPCC_ICRH;uiChannelShift= uiChannel – 32;}
ACNTSize = byteCount%BIDX;
if(ACNTSize != 0){//second PaRAMbyteCount -= ACNTSize;
unsigned int srcAddress2 = srcAddress + ACNTSize;unsigned int dstAddress2 = dstAddress + ACNTSize;uiChannel2 = uiChannel+1;
uiBCNT = byteCount/BIDX;if(uiBCNT>65535)uiBCNT= 65535;
if(uiBCNT != 0){EDMACCRegs->PARAMSET[uiChannel2].OPT=CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, //Intermediate transfer completion chainingCSL_EDMA3_TCCH_DIS, //Transfer complete chainingCSL_EDMA3_ITCINT_DIS, //Intermediate transfer completion interruptCSL_EDMA3_TCINT_EN, //Transfer complete interruptuiChannel2, //Transfer complete code(TCC): 6-bit code sets the relevant bit in the chaining enable register(CER) for chaining or in the interrupt pending register(IPR) for interrupts.CSL_EDMA3_TCC_NORMAL, //TCC modeCSL_EDMA3_FIFOWIDTH_NONE, //FIFO WidthCSL_EDMA3_STATIC_DIS, //keep PARAM unchargedCSL_EDMA3_SYNC_A, //A synchronizationCSL_EDMA3_ADDRMODE_INCR, //Destination address mode //1CSL_EDMA3_ADDRMODE_INCR); //Source address mode //1EDMACCRegs->PARAMSET[uiChannel2].SRC= GLOBAL_ADDR(srcAddress2);EDMACCRegs->PARAMSET[uiChannel2].SRC_DST_BIDX= CSL_EDMA3_BIDX_MAKE(BIDX, BIDX); //BIDX range from -32768 to 32767EDMACCRegs->PARAMSET[uiChannel2].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF, 0); //0xFFFF is specified a null linkEDMACCRegs->PARAMSET[uiChannel2].SRC_DST_CIDX= CSL_EDMA3_CIDX_MAKE(0,0);EDMACCRegs->PARAMSET[uiChannel2].CCNT= 1;EDMACCRegs->PARAMSET[uiChannel2].A_B_CNT= CSL_EDMA3_CNT_MAKE(BIDX, uiBCNT); //BCNT is between 1 to 65535EDMACCRegs->PARAMSET[uiChannel2].DST= GLOBAL_ADDR(dstAddress2);
}
EDMACCRegs->PARAMSET[uiChannel].OPT=CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, //Intermediate transfer completion chainingCSL_EDMA3_TCCH_DIS, //Transfer complete chainingCSL_EDMA3_ITCINT_DIS, //Intermediate transfer completion interruptCSL_EDMA3_TCINT_EN, //Transfer complete interruptuiChannel, //Transfer complete code(TCC): 6-bit code sets the relevant bit in the chaining enable register(CER) for chaining or in the interrupt pending register(IPR) for interrupts.CSL_EDMA3_TCC_NORMAL, //TCC modeCSL_EDMA3_FIFOWIDTH_NONE, //FIFO WidthCSL_EDMA3_STATIC_DIS, //keep PARAM updatedCSL_EDMA3_SYNC_A, //AB synchronizationCSL_EDMA3_ADDRMODE_INCR, //Destination address mode //1CSL_EDMA3_ADDRMODE_INCR); //Source address mode //1EDMACCRegs->PARAMSET[uiChannel].SRC= GLOBAL_ADDR(srcAddress);EDMACCRegs->PARAMSET[uiChannel].SRC_DST_BIDX= CSL_EDMA3_BIDX_MAKE(0, 0); //BIDX range from -32768 to 32767EDMACCRegs->PARAMSET[uiChannel].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0x4020, 0); //0xFFFF is specified a null linkEDMACCRegs->PARAMSET[uiChannel].SRC_DST_CIDX= CSL_EDMA3_CIDX_MAKE(0,0);EDMACCRegs->PARAMSET[uiChannel].CCNT= 1;EDMACCRegs->PARAMSET[uiChannel].A_B_CNT= CSL_EDMA3_CNT_MAKE(ACNTSize, 1);EDMACCRegs->PARAMSET[uiChannel].DST= GLOBAL_ADDR(dstAddress);
//Manually trigger the EDMA//(*TPCC_ESR)= 1<<(uiChannelShift);
//wait for completion//while(0==((*TPCC_IPR)&(1<<(uiChannelShift))));
//clear completion flag//(*TPCC_ICR)= 1<<(uiChannelShift);
}}
Chia-Hung Chen1：
回复 Chia-Hung Chen1:
上述的2個函式單核和多核測試正確性都沒問題, 單核執行時間是正常的, 但多核同時跑的時候, 執行時間卻會隨核心數目加倍, 此問題還要待解決! 我心須先把TCCH關掉, 用正規的ESR觸發2次來啟動link傳輸, 看看多核是否速度仍是變慢, 待測試
