TI中文支持网使用F28335 McBSP SPI功能 发送数据配置为20位 如果第二十位数据位低电平 第二十位数据发送完毕后到下一次发送数据前 波形不能一直保持低电平 会出现拉高现象 如图
请问这是什么原因造成的？
McBSP SPI寄存器配置如下：
void init_mcbsp_spi(void)
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F00; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.RCR2.bit.RDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.RCR1.bit.RWDLEN1=3; // 32-bit word
McbspaRegs.XCR1.bit.XWDLEN1=3; // 32-bit word
McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspaRegs.SRGR1.all= 0x0007; // Frame Width = 1 CLKG period, CLKGDV=16
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
发送数据函数如下
void SendData(Uint16 addr, Uint16 config)
{
Uint32 databuf=0x00000000;
Uint16 sdata1 = 0x000; // Sent Data
Uint16 sdata2 = 0x000; // Sent Data
databuf=config;
databuf<<=3;
databuf|=(addr&0x00000007);
//databuf<<=1;
//databuf|=1;
sdata1=(Uint16)(databuf&0x0000ffff);
sdata2=(Uint16)((databuf>>16)&0x0000ffff);
mcbsp_xmit(sdata1,sdata2);
while( McbspaRegs.SPCR2.bit.XEMPTY == 0 );
}
void mcbsp_xmit(int a, int b)
{
McbspaRegs.DXR2.all=b;
McbspaRegs.DXR1.all=a;
}
mangui zhang：
是不是每次启动发送数据时都默认为高啊 所以会被拉高
不确定 啊 MCBSP没有配置为SPI使用过
使用F28335 McBSP SPI功能 发送数据配置为20位 如果第二十位数据位低电平 第二十位数据发送完毕后到下一次发送数据前 波形不能一直保持低电平 会出现拉高现象 如图
请问这是什么原因造成的？
McBSP SPI寄存器配置如下：
void init_mcbsp_spi(void)
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F00; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.RCR2.bit.RDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.RCR1.bit.RWDLEN1=3; // 32-bit word
McbspaRegs.XCR1.bit.XWDLEN1=3; // 32-bit word
McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspaRegs.SRGR1.all= 0x0007; // Frame Width = 1 CLKG period, CLKGDV=16
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}
发送数据函数如下
void SendData(Uint16 addr, Uint16 config)
{
Uint32 databuf=0x00000000;
Uint16 sdata1 = 0x000; // Sent Data
Uint16 sdata2 = 0x000; // Sent Data
databuf=config;
databuf<<=3;
databuf|=(addr&0x00000007);
//databuf<<=1;
//databuf|=1;
sdata1=(Uint16)(databuf&0x0000ffff);
sdata2=(Uint16)((databuf>>16)&0x0000ffff);
mcbsp_xmit(sdata1,sdata2);
while( McbspaRegs.SPCR2.bit.XEMPTY == 0 );
}
void mcbsp_xmit(int a, int b)
{
McbspaRegs.DXR2.all=b;
McbspaRegs.DXR1.all=a;
}
Feng Youkui Feng Youkui：
回复 mangui zhang:
不是 正常的如果是低应该保持低才对 没找到什么原因
