TI中文支持网首先我的程序目的是实现fpga通过srio将数据传输给dsp，传输结束发送doorbell中断，而后通过omp并行编程将数据处理分到core1-core7上进行计算。
本程序以PDK生成的SRIO_LpbkDioIsr_evmc6678_C66BiosExampleProject为基础进行修改，之前参考过很多帖子，由于srio要使用qmss而omp也要使用qmss所以按照http://downloads.ti.com/mctools/esd/docs/openmp-dsp/integrating_apps_with_qmss.html 给出的方式进行手动初始化qmss，由于srio要用128个descriptor，且使用Qmss_MemRegion_MEMORY_REGION0，所以在cfg文件中将下列几项进行修改
ompSettings.runtimeInitializesQmss = false;
OpenMP.qmssMemRegionIndex = 1;
OpenMP.qmssFirstDescIdxInLinkingRam = 128;
同时对按照user guide里的操作将cache进行配置
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(msmcNcVirt.base, msmcNcVirt.len, 0);
Cache.setMarMeta(OpenMP.ddrBase, OpenMP.ddrSize, Cache.PC|Cache.PFX|Cache.WTE);
Cache.setMarMeta(OpenMP.msmcBase, OpenMP.msmcSize, Cache.PC|Cache.PFX|Cache.WTE);
并在omp启动的函数前将自己写的qmss函数执行
Startup.lastFxns.$add('&qmssInitOmp');
Startup.lastFxns.$add('&__TI_omp_initialize_rtsc_mode');
以上均按照user guide和https://e2e.ti.com/support/processors/f/791/t/468231?OpenMP-QMSS-manual-setup#pi320966=1
现有如下现象：
1 若不启动srio的task则omp程序运行正常；
2 若不启动omp程序则srio程序运行正常，并且能收到doorbell中断；
3 若同时启动srio程序和omp程序，则在srio程序依旧能收到doorbell中断，但是omp程序报错INTERNAL ERROR: Unexpected NULL pointer – src/tomp_parallel.c, 224
我的task通过cfg文件进行静态启动，srio的优先级最低，omp程序的优先级最高，严格按照上述链接中的指导进行，比如将auto run options 进行了相应修改。
我的疑问是：
1 我的qmss启动方式是否正确；
2 什么时候omp程序会出现这种报错INTERNAL ERROR: Unexpected NULL pointer – src/tomp_parallel.c, 224；
下面贴出我的cfg 文件和相关代码
user6224283：
app.cfg文件/** Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/*All rights reserved.**Redistribution and use in source and binary forms, with or without*modification, are permitted provided that the following conditions are met:** Redistributions of source code must retain the above copyright*notice, this list of conditions and the following disclaimer.** Redistributions in binary form must reproduce the above copyright*notice, this list of conditions and the following disclaimer in the*documentation and/or other materials provided with the distribution.** Neither the name of Texas Instruments Incorporated nor the*names of its contributors may be used to endorse or promote products*derived from this software without specific prior written permission.** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE* POSSIBILITY OF SUCH DAMAGE.*//***************************/
/* SECTION MAPPING*/
/***************************/
/* Load the CSL package */
var Csl=xdc.loadPackage('ti.csl');/* Load the CPPI package */
var Cppi=xdc.loadPackage('ti.drv.cppi');/* Load the QMSS package */
var Qmss=xdc.loadPackage('ti.drv.qmss');
var srio=xdc.loadPackage('ti.drv.srio');
/* Load and configure SYSBIOS packages */
var BIOS= xdc.useModule('ti.sysbios.BIOS');
var Task= xdc.useModule('ti.sysbios.knl.Task');
var Clock= xdc.useModule('ti.sysbios.knl.Clock');
var Mailbox= xdc.useModule('ti.sysbios.knl.Mailbox');var Hwi= xdc.useModule('ti.sysbios.hal.Hwi');
var Ecm= xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
var BiosCache = xdc.useModule('ti.sysbios.hal.Cache');
var HeapBuf= xdc.useModule('ti.sysbios.heaps.HeapBuf');
var HeapMem= xdc.useModule('ti.sysbios.heaps.HeapMem');
var Exc= xdc.useModule('ti.sysbios.family.c64p.Exception');
var Cache= xdc.useModule('ti.sysbios.family.c66.Cache');BIOS.taskEnabled = true;
Task.common$.namedInstance = true;
var program = xdc.useModule('xdc.cfg.Program');program.sectMap[".args"]= new Program.SectionSpec();
program.sectMap[".bss"]= new Program.SectionSpec(); //
program.sectMap[".cinit"]= new Program.SectionSpec(); //
program.sectMap[".cio"]= new Program.SectionSpec(); //
program.sectMap[".const"]= new Program.SectionSpec(); //
program.sectMap[".data"]= new Program.SectionSpec();program.sectMap[".far"]= new Program.SectionSpec(); //
program.sectMap[".fardata"]= new Program.SectionSpec(); //
program.sectMap[".neardata"]= new Program.SectionSpec(); //
program.sectMap[".rodata"]= new Program.SectionSpec(); //
program.sectMap[".stack"]= new Program.SectionSpec(); //
program.sectMap[".switch"]= new Program.SectionSpec(); //
program.sectMap[".sysmem"]= new Program.SectionSpec();
program.sectMap[".text"]= new Program.SectionSpec(); //
Program.sectMap[".inputbuff"]= new Program.SectionSpec(); // add when will deal with buffer alloocation// Must place these sections in core local memoryprogram.sectMap[".args"].loadSegment= "L2SRAM";
program.sectMap[".cio"].loadSegment= "L2SRAM";// Variables in the following data sections can potentially be 'shared' in
// OpenMP. These sections must be placed in shared memory.
program.sectMap[".bss"].loadSegment= "DDR3";
program.sectMap[".cinit"].loadSegment= "DDR3";
program.sectMap[".const"].loadSegment= "DDR3";
program.sectMap[".data"].loadSegment= "DDR3";
program.sectMap[".far"].loadSegment= "DDR3";
program.sectMap[".fardata"].loadSegment= "DDR3";
program.sectMap[".neardata"].loadSegment= "DDR3";
program.sectMap[".rodata"].loadSegment= "DDR3";
program.sectMap[".sysmem"].loadSegment= "DDR3";
Program.sectMap[".inputbuff"].loadSegment= "MSMCSRAM";// Code sections shared by cores - place in shared memory to avoid duplication
program.sectMap[".switch"].loadSegment= program.platform.codeMemory;
program.sectMap[".text"].loadSegment= program.platform.codeMemory;// Size the default stack and place it in L2SRAMprogram.stack = 0x20000;
program.sectMap[".stack"].loadSegment= "L2SRAM";// Since there are no arguments passed to main, set .args size to 0
program.argSize = 0;// Send System_printf output to the same place as printf
var System = xdc.useModule('xdc.runtime.System');
var SysStd = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;/********************************/
/* OPENMP RUNTIME CONFIGURATION */
/********************************/// Include OMP runtime in the build
var ompSettings = xdc.useModule("ti.runtime.openmp.Settings");// Set to true if the application uses or has dependencies on BIOS components
ompSettings.usingRtsc = true;
ompSettings.runtimeInitializesQmss=false;if (ompSettings.usingRtsc)
{/* Configure OpenMP for BIOS* - OpenMP.configureCores(masterCoreId, numberofCoresInRuntime)*Configures the id of the master core and the number of cores*available to the runtime.*/var OpenMP = xdc.useModule('ti.runtime.ompbios.OpenMP');// Configure the index of the master core and the number of cores available// to the runtime. The cores are contiguous.OpenMP.masterCoreIdx = 0;OpenMP.qmssMemRegionIndex = 1;//4; //1OpenMP.qmssFirstDescIdxInLinkingRam = 128;//224; //160// Setup number of cores based on the devicevar deviceName = String(Program.cpu.deviceName);if(deviceName.search("6670") != -1) { OpenMP.numCores= 4; }else if (deviceName.search("6657") != -1) { OpenMP.numCores= 2; }else{ OpenMP.numCores= 8; }// Pull in memory ranges described in Platform.xdc to configure the runtimevar ddr3= Program.cpu.memoryMap["DDR3"];var msmc= Program.cpu.memoryMap["MSMCSRAM"];var msmcNcVirt = Program.cpu.memoryMap["OMP_MSMC_NC_VIRT"];var msmcNcPhy= Program.cpu.memoryMap["OMP_MSMC_NC_PHY"];// Initialize the runtime with memory range informationOpenMP.msmcBase = msmc.base;OpenMP.msmcSize = msmc.len;OpenMP.msmcNoCacheVirtualBase= msmcNcVirt.base;OpenMP.msmcNoCacheVirtualSize= msmcNcVirt.len;OpenMP.msmcNoCachePhysicalBase= msmcNcPhy.base;OpenMP.ddrBase= ddr3.base;OpenMP.ddrSize= ddr3.len;var Cache= xdc.useModule('ti.sysbios.family.c66.Cache');Cache.setMarMeta(msmcNcVirt.base, msmcNcVirt.len, 0);Cache.setMarMeta(OpenMP.ddrBase, OpenMP.ddrSize,Cache.PC|Cache.PFX|Cache.WTE);Cache.setMarMeta(OpenMP.msmcBase, OpenMP.msmcSize,Cache.PC|Cache.PFX|Cache.WTE);// Configure memory allocation using HeapOMP// HeapOMP handles// - Memory allocation requests from BIOS components (core local memory)// - Shared memory allocation by utilizing the IPC module to enable//multiple cores to allocate memory out of the same heap - used by mallocvar HeapOMP = xdc.useModule('ti.runtime.ompbios.HeapOMP');// Shared Region 0 must be initialized for IPCvar sharedRegionId = 0;// Size of the core local heapvar localHeapSize= 0x8000;// Size of the heap shared by all the coresvar sharedHeapSize = 0x8000000;// Initialize a Shared Region & create a heap in the DDR3 memory regionvar SharedRegion= xdc.useModule('ti.sdo.ipc.SharedRegion');SharedRegion.setEntryMeta( sharedRegionId,{base: ddr3.base,len:sharedHeapSize,ownerProcId: 0,cacheEnable: true,createHeap: true,isValid: true,name: "DDR3_SR0",});// Configure and setup HeapOMPHeapOMP.configure(sharedRegionId, localHeapSize);// The function __TI_omp_reset_rtsc_mode must be called after resetvar Reset = xdc.useModule('xdc.runtime.Reset');Reset.fxns.$add('&__TI_omp_reset_rtsc_mode');// __TI_omp_start_rtsc_mode configures the runtime and calls mainvar Startup = xdc.useModule('xdc.runtime.Startup');Startup.lastFxns.$add('&qmssInitOmp');Startup.lastFxns.$add('&__TI_omp_initialize_rtsc_mode');
}
else
{/* Size the heap. It must be placed in shared memory */program.heap = sharedHeapSize;
}
var Task =xdc.useModule('ti.sysbios.knl.Task');
/*
var task0Params = new Task.Params();
task0Params.instance.name = "task0";
task0Params.priority=15;
Program.global.task0 = Task.create('&dioExampleTask', task0Params);*/var task2Params = new Task.Params();
task2Params.instance.name="taskDio";
task2Params.priority=10;
Program.global.taskDio=Task.create("&dioExampleTask",task2Params);var task1Params = new Task.Params();
task1Params.instance.name = "task1";
task1Params.priority=15;
Program.global.task1 = Task.create('&FxnEx2', task1Params);var task0Params = new Task.Params();
task0Params.instance.name = "task0";
task0Params.priority=11;
Program.global.task0 = Task.create('&FxnZh', task0Params);
user6224283：
回复 user6224283:
下面是我的main.c,我的程序执行顺序按照cfg是先配置qmss，然后启动omp，最后创建3个task
user6224283：
回复 user6224283:
/***@fileloopbackDioIsr.c**@brief*This is an example application which shows how DIO transfer*completion interrupts can be registered and serviced.**\par*NOTE:*(C) Copyright 2010-2012 Texas Instruments, Inc.**Redistribution and use in source and binary forms, with or without*modification, are permitted provided that the following conditions*are met:**Redistributions of source code must retain the above copyright*notice, this list of conditions and the following disclaimer.**Redistributions in binary form must reproduce the above copyright*notice, this list of conditions and the following disclaimer in the*documentation and/or other materials provided with the*distribution.**Neither the name of Texas Instruments Incorporated nor the names of*its contributors may be used to endorse or promote products derived*from this software without specific prior written permission.**THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS*"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT*LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR*A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT*OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,*SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT*LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,*DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY*THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT*(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.**\par */ #include <ti/runtime/openmp/omp.h> #include <xdc/std.h> #include <string.h> #include <c6x.h> #include <xdc/runtime/IHeap.h> #include <xdc/runtime/System.h> #include <xdc/runtime/Error.h> #include <xdc/runtime/Memory.h> #include <ti/sysbios/BIOS.h> #include <ti/sysbios/knl/Task.h> #include <ti/sysbios/heaps/HeapBuf.h> #include <ti/sysbios/heaps/HeapMem.h> #include <ti/sysbios/family/c64p/Hwi.h> #include <ti/sysbios/family/c64p/EventCombiner.h> #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>/* IPC includes */ #include <ti/ipc/GateMP.h> #include <ti/ipc/Ipc.h> #include <ti/ipc/ListMP.h> #include <ti/ipc/SharedRegion.h> #include <ti/ipc/MultiProc.h>#include <xdc/cfg/global.h>/* SRIO Driver Include File. */ #include <ti/drv/srio/srio_drv.h> #include <ti/drv/srio/srio_osal.h>/* CPPI/QMSS Include Files. */ #include <ti/drv/cppi/cppi_drv.h> #include <ti/drv/qmss/qmss_drv.h> #include <ti/drv/qmss/qmss_firmware.h>/* CSL Chip Functional Layer */ #include <ti/csl/csl_chip.h>/* CSL Cache Functional Layer */ #include <ti/csl/csl_cacheAux.h>/* PSC CSL Include Files */ #include <ti/csl/csl_psc.h> #include <ti/csl/csl_pscAux.h>/* CSL SRIO Functional Layer */ #include <ti/csl/csl_srio.h> #include <ti/csl/csl_srioAux.h>/* CSL CPINTC Include Files. */ #include <ti/csl/csl_cpIntc.h>/* Platform Specific Include Files */ #include "srioPlatCfg.h" #include "MTD_Pack/omp_hello.h" #include "RCSHeader.h" #include "KeyStone_EMIF16_init.h" #if !defined(CSL_CIC0_SRIO_INTDST0) #define CSL_CIC0_SRIO_INTDST0CSL_INTC0_INTDST0 #endif/************************************************************************************************ LOCAL Definitions ***********************************************************************************************//* This is the Number of host descriptors which are available & configured* in the memory region for this example. */ #define NUM_HOST_DESC128/* This is the size of each descriptor. */ #define SIZE_HOST_DESC48/* MTU of the SRIO Driver. We are currently operating @ MTU of 256 bytes. */ #define SRIO_MAX_MTU256/* This is the size of the data buffer which is used for DIO Sockets. */ #define SIZE_DIO_PACKET128/* Defines the core number responsible for system initialization. */ #define CORE_SYS_INIT0/* Defines number of DIO sockets used in this example */ #define SRIO_DIO_LSU_ISR_NUM_SOCKETS3/* Defines number of transfers done by DIO sockets in this example */ #define SRIO_DIO_LSU_ISR_NUM_TRANSFERS3/* ISR timeout value (in cycles) used in this example */ #define SRIO_DIO_LSU_ISR_TIMEOUT100000/************************************************************************************************ Global Variables ************************************************************************************************//* Memory allocated for the descriptors. This is 16 bit aligned. */ #pragma DATA_ALIGN (host_region, 16) Uint8host_region[NUM_HOST_DESC * SIZE_HOST_DESC];/* Memory used for the accumulator list. */ #pragma DATA_ALIGN (gHiPriAccumList, 16) UInt32gHiPriAccumList[64];/* Global SRIO and QMSS Configuration */ Qmss_InitCfgqmssInitConfig;/* Global Varialble which keeps track of the core number executing the* application. */ UInt32coreNum = 0xFFFF;/* Shared Memory Variable to ensure synchronizing SRIO initialization* with all the other cores. */ /* Created an array to pad the cache line with SRIO_MAX_CACHE_ALIGN size */ #pragma DATA_ALIGN(isSRIOInitialized, 128) #pragma DATA_SECTION (isSRIOInitialized, ".srioSharedMem"); volatile Uint32isSRIOInitialized[(SRIO_MAX_CACHE_ALIGN / sizeof(Uint32))] = { 0 };Srio_DrvHandlehDrvManagedSrioDrv;CSL_SrioHandlehSrioCSL;/* These are the device identifiers used in the Example Application */ //const uint32_t DEVICE_ID1_16BIT= 0xBEEF; //const uint32_t DEVICE_ID1_8BIT= 0xAB; //const uint32_t DEVICE_ID2_16BIT= 0x4560; //const uint32_t DEVICE_ID2_8BIT= 0xCD; //const uint32_t DEVICE_ID3_16BIT= 0x1234; //const uint32_t DEVICE_ID3_8BIT= 0x12; //const uint32_t DEVICE_ID4_16BIT= 0x5678; //const uint32_t DEVICE_ID4_8BIT= 0x56;const uint32_t DEVICE_ID1_16BIT= 0x00AB; const uint32_t DEVICE_ID1_8BIT= 0xAB; const uint32_t DEVICE_ID2_16BIT= 0x00AB; const uint32_t DEVICE_ID2_8BIT= 0xAB; const uint32_t DEVICE_ID3_16BIT= 0x00AB; const uint32_t DEVICE_ID3_8BIT= 0xAB; const uint32_t DEVICE_ID4_16BIT= 0x00AB; const uint32_t DEVICE_ID4_8BIT= 0xAB; /* Array containing SRIO socket handles */ Srio_SockHandle srioSocket[SRIO_DIO_LSU_ISR_NUM_SOCKETS];/* Source and Destination Data Buffers (payload buffers) */ UInt8* srcDataBuffer[SRIO_DIO_LSU_ISR_NUM_SOCKETS * SRIO_DIO_LSU_ISR_NUM_TRANSFERS]; UInt8* dstDataBuffer[SRIO_DIO_LSU_ISR_NUM_SOCKETS * SRIO_DIO_LSU_ISR_NUM_TRANSFERS];/* Global debug variable to track number of ISRs raised */ volatile UInt32 srioDbgDioIsrCnt = 0;/* Global variable to indicate completion of ISR processing */ volatile UInt32 srioLsuIsrServiced = 0;/* Global variables to count good and bad transfers */ volatile UInt32 srioDioLsuGoodTransfers = 0; volatile UInt32 srioDioLsuBadTransfers= 0;/*********************************************************************************************** Extern Definitions ***********************************************************************************************/extern UInt32 malloc_counter; extern UInt32 free_counter;extern int32_t SrioDevice_init (void);/* QMSS device specific configuration */ extern Qmss_GlobalConfigParamsqmssGblCfgParams;/* CPPI device specific configuration */ extern Cppi_GlobalConfigParamscppiGblCfgParams;/* OSAL Data Buffer Memory Initialization. */ extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize);/* Enable Time Stamp Counter */ extern void CSL_tscEnable(void);/********************************************************************************************** SRIO EXAMPLE FUNCTIONS ********************************************************************************************//***@b Description*@n*Utility function which converts a local address to global.**@param[in]addr*Local address to be converted**@retval*Global Address*/ unsigned int Convert_CoreLocal2GlobalAddr (unsigned intaddr// L2 address to be converted to global ) {unsigned int coreNum;// Get the core numbercoreNum = CSL_chipReadReg(CSL_CHIP_DNUM);// Compute the global address.return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff)); }static Int32 enable_srio (void) { #ifndef SIMULATOR_SUPPORT/* SRIO power domain is turned OFF by default. It needs to be turned on before doing any* SRIO device register access. This not required for the simulator. *//* Set SRIO Power domain to ON */CSL_PSC_enablePowerDomain (CSL_PSC_PD_SRIO);/* Enable the clocks too for SRIO */CSL_PSC_setModuleNextState (CSL_PSC_LPSC_SRIO, PSC_MODSTATE_ENABLE);/* Start the state transition */CSL_PSC_startStateTransition (CSL_PSC_PD_SRIO);/* Wait until the state transition process is completed. */while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_SRIO));/* Return SRIO PSC status */if ((CSL_PSC_getPowerDomainState(CSL_PSC_PD_SRIO) == PSC_PDSTATE_ON) &&(CSL_PSC_getModuleState (CSL_PSC_LPSC_SRIO) == PSC_MODSTATE_ENABLE)){/* SRIO ON. Ready for use */return 0;}else{/* SRIO Power on failed. Return error */return -1;} #else/* PSC is not supported on simulator. Return success always */return 0; #endif }/***@b Description*@n*System Initialization Code. This is added here only for illustrative*purposes and needs to be invoked once during initialization at*system startup.**@retval*Success-0*@retval*Error-<0*/void initCPPI(){ ///* Initialize CPPI CPDMA */int result;result = Cppi_init (&cppiGblCfgParams);if (result != CPPI_SOK){System_printf ("Error initializing Queue Manager SubSystem error code : %d\n", result);return -1;}/* CPPI and Queue Manager are initialized. */System_printf ("Debug(Core %d): Queue Manager and CPPI are initialized.\n", coreNum);System_printf ("Debug(Core %d): Host Region 0x%x\n", coreNum, host_region);return 0; } int qmssInitOmp (void) {intwc;intresult = 0;Qmss_MemRegInfomemCfg;Cppi_DescCfgcppiDescCfg;unsigned intnumAllocated;Qmss_InitCfgqmssInitConfig;Qmss_QueueHndgGlobalFreeQHnd;// Set up QMSS configurationif (DNUM==0){memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));// Use internal linking RAMqmssInitConfig.linkingRAM0Base=0;qmssInitConfig.linkingRAM0Size=0;qmssInitConfig.linkingRAM1Base=0x0;qmssInitConfig.maxDescNum=NUM_HOST_DESC+256;qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);// Initialize the Queue Managerresult = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);if(result != QMSS_SOK) {#if DEBUG_ERRORSSystem_printf("Error initializing Queue Manager SubSystem, Error code : %d\n", result);#endif // DEBUG_ERRORSreturn -1;}// Initialize and setup CPSW Host Descriptorsmemset (host_region, 0, SIZE_HOST_DESC * NUM_HOST_DESC);memCfg.descBase=(unsigned int *) Convert_CoreLocal2GlobalAddr ((unsigned int) host_region);memCfg.descSize=SIZE_HOST_DESC;memCfg.descNum=NUM_HOST_DESC;memCfg.manageDescFlag=Qmss_ManageDesc_MANAGE_DESCRIPTOR;memCfg.memRegion=Qmss_MemRegion_MEMORY_REGION0;memCfg.startIndex=0;// Insert Host Descriptor memory regionresult = Qmss_insertMemoryRegion(&memCfg);if(result == QMSS_MEMREGION_ALREADY_INITIALIZED) {#if DEBUG_ERRORSSystem_printf("Memory Region %d already Initialized \n", memCfg.memRegion);#endif // DEBUG_ERRORS} else if(result < QMSS_SOK) {#if DEBUG_ERRORSSystem_printf("Error: Inserting memory region for Eth %d, Error code : %d\n", memCfg.memRegion, result);#endif // DEBUG_ERRORSreturn -1;}///* Initialize all the descriptors we just allocated on the //* memory region above. Setup the descriptors with some well //* known values before we use them for data transfers. //*/ //memset (&cppiDescCfg, 0, sizeof (cppiDescCfg)); //cppiDescCfg.memRegion=Qmss_MemRegion_MEMORY_REGION0; //cppiDescCfg.descNum=NUM_HOST_DESC; //cppiDescCfg.destQueueNum=QMSS_PARAM_NOT_SPECIFIED; //cppiDescCfg.queueType=Qmss_QueueType_GENERAL_PURPOSE_QUEUE; //cppiDescCfg.initDesc=Cppi_InitDesc_INIT_DESCRIPTOR; //cppiDescCfg.descType=Cppi_DescType_HOST; // ///* By default: //*(1) Return descriptors to tail of queue //*(2) Always return entire packet to this free queue //*(3) Set that PS Data is always present in start of SOP buffer //*(4) Configure free q num < 4K, hence qMgr = 0 //*(5) Recycle back to the same Free queue by default. //*/ //cppiDescCfg.returnPushPolicy=Qmss_Location_TAIL; //cppiDescCfg.cfg.host.returnPolicy=Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET; //cppiDescCfg.cfg.host.psLocation=Cppi_PSLoc_PS_IN_DESC; //cppiDescCfg.returnQueue.qMgr=0; //cppiDescCfg.returnQueue.qNum=QMSS_PARAM_NOT_SPECIFIED; //cppiDescCfg.epibPresent=Cppi_EPIB_EPIB_PRESENT; // //// Initialize the descriptors, create a free queue and push descriptors to a global free queue //if((gGlobalFreeQHnd = Cppi_initDescriptor (&cppiDescCfg, &numAllocated)) <= 0) { //#if DEBUG_ERRORS //System_printf("Error Initializing Free Descriptors, Error: %d \n", gGlobalFreeQHnd); //#endif // DEBUG_ERRORS //return -1; //}initCPPI();Qmss_start();System_printf("QMSS initialized by application\n");}return 0; } Int32 system_init (Void) {Int32result;Qmss_MemRegInfomemRegInfo;coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);if(DNUM==0){/* Initialize the QMSS Configuration block. */memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));/* Initialize the Host Region. */memset ((void *)&host_region, 0, sizeof(host_region));/* Set up the linking RAM. Use the internal Linking RAM.* LLD will configure the internal linking RAM address and maximum internal linking RAM size if* a value of zero is specified. Linking RAM1 is not used */qmssInitConfig.linkingRAM0Base = 0;qmssInitConfig.linkingRAM0Size = 0;qmssInitConfig.linkingRAM1Base = 0;qmssInitConfig.maxDescNum= NUM_HOST_DESC+256;#ifdef xdc_target__bigEndian/* PDSP Configuration: Big Endian */qmssInitConfig.pdspFirmware[0].pdspId= Qmss_PdspId_PDSP1;qmssInitConfig.pdspFirmware[0].firmware = &acc48_be;qmssInitConfig.pdspFirmware[0].size= sizeof (acc48_be);#else/* PDSP Configuration: Little Endian */qmssInitConfig.pdspFirmware[0].pdspId= Qmss_PdspId_PDSP1;qmssInitConfig.pdspFirmware[0].firmware = &acc48_le;qmssInitConfig.pdspFirmware[0].size= sizeof (acc48_le);#endif/* Initialize Queue Manager Sub System */result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);if (result != QMSS_SOK){System_printf ("Error initializing Queue Manager SubSystem error code : %d\n", result);return -1;}/* Start the QMSS. */if (Qmss_start() != QMSS_SOK){System_printf ("Error: Unable to start the QMSS\n");return -1;}/* Memory Region 0 Configuration */memRegInfo.descBase= (unsigned int *) Convert_CoreLocal2GlobalAddr ((unsigned int) host_region);memRegInfo.descSize= SIZE_HOST_DESC;memRegInfo.descNum= NUM_HOST_DESC;memRegInfo.manageDescFlag= Qmss_ManageDesc_MANAGE_DESCRIPTOR; //memRegInfo.memRegion= Qmss_MemRegion_MEMORY_REGION_NOT_SPECIFIED;memRegInfo.memRegion= Qmss_MemRegion_MEMORY_REGION0;memRegInfo.startIndex=0;/* Initialize and inset the memory region. */result = Qmss_insertMemoryRegion (&memRegInfo);if (result < QMSS_SOK){System_printf ("Error inserting memory region: %d\n", result);return -1;}/* Initialize CPPI CPDMA */result = Cppi_init (&cppiGblCfgParams);if (result != CPPI_SOK){System_printf ("Error initializing Queue Manager SubSystem error code : %d\n", result);return -1;}/* CPPI and Queue Manager are initialized. */System_printf ("Debug(Core %d): Queue Manager and CPPI are initialized.\n", coreNum);System_printf ("Debug(Core %d): Host Region 0x%x\n", coreNum, host_region);return 0;}}unsigned long longdoorbell_rev_core = 0; void myDoorbellCompletionIsr(UArg argument) {CSL_SRIO_ClearDoorbellPendingInterrupt (hSrioCSL, 0, 0xFFFF);CSL_SRIO_ClearLSUPendingInterrupt (hSrioCSL, 0xFFFFFFFF, 0xFFFFFFFF);doorbell_rev_core = doorbell_rev_core + 1;//Semaphore_post(sem0);//isDoorBellIsr= 1;return;} Void dioExampleTask(UArg arg0, UArg arg1){ #ifdef SIMULATOR_SUPPORT #warn SRIO DIO LSU ISR example is not supported on SIMULATOR !!!System_printf ("SRIO DIO LSU ISR example is not supported on SIMULATOR. Exiting!\n");return; #elseSystem_printf ("Executing the SRIO DIO example on the DEVICE\n"); #endif/* Initialize the system only if the core was configured to do so. */if (coreNum == CORE_SYS_INIT){System_printf ("Debug(Core %d): System Initialization for CPPI & QMSS\n", coreNum);/* System Initialization */ //if (system_init() < 0) //return;/* Power on SRIO peripheral before using it */if (enable_srio () < 0){System_printf ("Error: SRIO PSC Initialization Failed\n");return;}/* Device Specific SRIO Initializations: This should always be called before* initializing the SRIO Driver. */if (SrioDevice_init() < 0)return;/* Initialize the SRIO Driver */if (Srio_init () < 0){System_printf ("Error: SRIO Driver Initialization Failed\n");return;}/* SRIO Driver is operational at this time. */System_printf ("Debug(Core %d): SRIO Driver has been initialized\n", coreNum);/* Write to the SHARED memory location at this point in time. The other cores cannot execute* till the SRIO Driver is up and running. */isSRIOInitialized[0] = 1;/* The SRIO IP block has been initialized. We need to writeback the cache here because it will* ensure that the rest of the cores which are waiting for SRIO to be initialized would now be* woken up. */CACHE_wbL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);}else{/* All other cores need to wait for the SRIO to be initialized before they proceed. */System_printf ("Debug(Core %d): Waiting for SRIO to be initialized.\n", coreNum);/* All other cores loop around forever till the SRIO is up and running.* We need to invalidate the cache so that we always read this from the memory. */while (isSRIOInitialized[0] == 0)CACHE_invL1d ((void *) &isSRIOInitialized[0], 128, CACHE_WAIT);/* Start the QMSS. */if (Qmss_start() != QMSS_SOK){System_printf ("Error: Unable to start the QMSS\n");return;}System_printf ("Debug(Core %d): SRIO can now be used.\n", coreNum);}System_printf("dio has entered\n");UInt8isAllocated;Srio_DrvConfigdrvCfg;/* Initialize the SRIO Driver Configuration. */memset ((Void *)&drvCfg, 0, sizeof(Srio_DrvConfig));/* Initialize the OSAL */if (Osal_dataBufferInitMemory(SRIO_MAX_MTU) < 0){System_printf ("Error: Unable to initialize the OSAL. \n");return;}/********************************************************************************* The SRIO Driver Instance is going to be created with the following properties:* - Driver Managed* - Interrupt Support (Pass the Rx Completion Queue as NULL)********************************************************************************//* Setup the SRIO Driver Managed Configuration. */drvCfg.bAppManagedConfig = FALSE;/* Driver Managed: Receive Configuration */drvCfg.u.drvManagedCfg.bIsRxCfgValid= 1;drvCfg.u.drvManagedCfg.rxCfg.rxMemRegion= Qmss_MemRegion_MEMORY_REGION0;drvCfg.u.drvManagedCfg.rxCfg.numRxBuffers= 4;drvCfg.u.drvManagedCfg.rxCfg.rxMTU= SRIO_MAX_MTU;/* Accumulator Configuration. */{int32_t coreToQueueSelector[4];/* This is the table which maps the core to a specific receive queue. */coreToQueueSelector[0] = 704;coreToQueueSelector[1] = 705;coreToQueueSelector[2] = 706;coreToQueueSelector[3] = 707;/* Since we are programming the accumulator we want this queue to be a HIGH PRIORITY Queue */drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE,coreToQueueSelector[coreNum], &isAllocated);if (drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue < 0){System_printf ("Error: Unable to open the SRIO Receive Completion Queue\n");return;}/* Accumulator Configuration is VALID. */drvCfg.u.drvManagedCfg.rxCfg.bIsAccumlatorCfgValid = 1;/* Accumulator Configuration. */drvCfg.u.drvManagedCfg.rxCfg.accCfg.channel= coreNum;drvCfg.u.drvManagedCfg.rxCfg.accCfg.command= Qmss_AccCmd_ENABLE_CHANNEL;drvCfg.u.drvManagedCfg.rxCfg.accCfg.queueEnMask= 0;drvCfg.u.drvManagedCfg.rxCfg.accCfg.queMgrIndex= coreToQueueSelector[coreNum];drvCfg.u.drvManagedCfg.rxCfg.accCfg.maxPageEntries= 2;drvCfg.u.drvManagedCfg.rxCfg.accCfg.timerLoadCount= 0;drvCfg.u.drvManagedCfg.rxCfg.accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;drvCfg.u.drvManagedCfg.rxCfg.accCfg.listEntrySize= Qmss_AccEntrySize_REG_D;drvCfg.u.drvManagedCfg.rxCfg.accCfg.listCountMode= Qmss_AccCountMode_ENTRY_COUNT;drvCfg.u.drvManagedCfg.rxCfg.accCfg.multiQueueMode= Qmss_AccQueueMode_SINGLE_QUEUE;/* Initialize the accumulator list memory *///memset ((Void *)&gHiPriAccumList[0], 0, sizeof(gHiPriAccumList));// drvCfg.u.drvManagedCfg.rxCfg.accCfg.listAddress = l2_global_address((UInt32)&gHiPriAccumList[0]);}/* Driver Managed: Transmit Configuration */drvCfg.u.drvManagedCfg.bIsTxCfgValid= 1;drvCfg.u.drvManagedCfg.txCfg.txMemRegion= Qmss_MemRegion_MEMORY_REGION0;drvCfg.u.drvManagedCfg.txCfg.numTxBuffers= 4;drvCfg.u.drvManagedCfg.txCfg.txMTU= SRIO_MAX_MTU;/* Start the Driver Managed SRIO Driver. */hDrvManagedSrioDrv = Srio_start(&drvCfg);if (hDrvManagedSrioDrv == NULL){System_printf ("Error(Core %d): SRIO Driver failed to start\n", coreNum);return;}/* Get the CSL SRIO Handle. */hSrioCSL = CSL_SRIO_Open (0);if (hSrioCSL == NULL)return -1;Hwi_ParamshwiParams;Hwi_HandlemyHwi;Error_Blockeb;Hwi_Params_init(&hwiParams);Error_init(&eb);hwiParams.arg= (UArg)hDrvManagedSrioDrv;hwiParams.eventId= 20; //myHwi = Hwi_create(11, (CpIntc_FuncPtr)myDoorbellCompletionIsr, &hwiParams, &eb);System_printf("Finish dispatch plug\n");} ///////////////////////////////////////////////////////////////////////////////void dac_source_dotfrq_config(double user_freq, double dds_freq,SignalSourceOut *signalSourceOut) {//u32 dds_freq = 312.5*1000000;if(user_freq >= 1.25*1000*1000*1000){return;}double ratio = user_freq/dds_freq;double pow2_30 = 1073741824;double phase_inc = pow2_30 * ratio;// 2^30 = 1073741824u32 phase_increment = phase_inc;u32 phase_offset =0;//phase_inc/8;signalSourceOut->dotfreq_phase_inc = phase_increment & 0x3fffffff;signalSourceOut->dotfreq_phase_offset = phase_offset & 0x3fffffff;}void dac_source_lfm_config(double fs, double pri, double pulsewidth, double bandwidth, double center_freq, unsigned int cpi_num, u32 dwg_startpos, u32 dwg_width_samples,SignalSourceOut *signalSourceOut) {u32 pri_samples = fs * pri;u32 pw_samples = fs * pulsewidth;double pow2_30 = 1073741824;double half_bandwidth = bandwidth/2.0;double phase_inc;u32 phase_inc_comp_size = 0;double ratio = (center_freq-half_bandwidth)/fs;u32 phase_inc_cfg;if(ratio <0){phase_inc_comp_size = - floor(ratio);phase_inc = (phase_inc_comp_size + ratio)*pow2_30;phase_inc_cfg = phase_inc;phase_inc_cfg = phase_inc_cfg & 0x3fffffff;}else {phase_inc_comp_size = 0;phase_inc = ratio*pow2_30;phase_inc_cfg = phase_inc;phase_inc_cfg = phase_inc_cfg & 0xffffffff;}double phase_inc_inc = pow2_30*bandwidth/(fs*fs*pulsewidth);u32 phase_inc_inc_cfg = phase_inc_inc;if(dwg_startpos + dwg_width_samples >pri_samples){return;//xil_printf("---The settings of door wave gate is out of range---\n\r");}if(dwg_width_samples > 8192){return;//xil_printf("---The settings of door wave gate width is out of range---\n\r");}signalSourceOut->lfm_pri_samples = pri_samples;signalSourceOut->lfm_pw_samples = pw_samples;signalSourceOut->lfm_initial_phase_inc = phase_inc_cfg;signalSourceOut->lfm_phase_inc_inc = phase_inc_inc_cfg & 0x00ffffff;signalSourceOut->lfm_cpi_num = cpi_num;signalSourceOut->lfm_dwg_startpos = dwg_startpos;signalSourceOut->lfm_dwg_samples = dwg_width_samples;System_printf("lfm_phase_inc_cfg = %x\n", signalSourceOut->lfm_initial_phase_inc);System_printf("lfm_phase_inc_inc_cfg = %x\n", signalSourceOut->lfm_phase_inc_inc);}void dac_source_config(u32 dac_source,SignalSourceOut *signalSourceOut) {u32 dac_source_cfg = 0x00000000;dac_source_cfg = dac_source_cfg | dac_source;signalSourceOut->dac_source_cfg = dac_source_cfg;}u32 target_dly_offset_config(double range, double fs) {double c= 3*1e8;double ratio = fs/c;double delay_offset = 2*range*ratio;u32 dly_offset = delay_offset;return dly_offset; }u32 target_doppler_phaseInc_config(double vel, double fs, double fc) {double c= 3*1e8;double wavelen = c/fc;double fd = 2*fabs(vel)/wavelen;//fd = 0.1*1e3;//for testingdouble factor = fd/fs;double pow2_30 = 1073741824;u32 phaseInc = pow2_30 * factor;return phaseInc; }void target_config(double target_vel, double target_range, double fs, double fc, SignalSourceOut *signalSourceOut) {//double fs = 180 *1e6;//double fc0 = 77;//77GHz//double fc1 = 1e9;u32target_delay_offset;target_delay_offset = target_dly_offset_config(target_range, fs);u32 target_doppler_phaseInc = target_doppler_phaseInc_config(target_vel, fs, fc);unsignedchar target_vel_negative = (target_vel < 0.0? 1:0);u32 target_config =target_delay_offset & 0x3ff;u32 target_dopplerphaseInc =(target_vel_negative & 0x01) <<31 |(target_doppler_phaseInc & 0x3fffffff);signalSourceOut->delay_config = target_config;signalSourceOut->doppler_config = target_dopplerphaseInc;} void setEmifValue() {int i = 0;SignalSourceOut signalSourceOut;convertSignalSource(signalSourceIn,(SignalSourceOut *)&signalSourceOut);System_printf("Converting \n");unsigned int *tmp;tmp = (unsigned int *)malloc(sizeof(SignalSourceOut));memcpy(tmp,(char *)&signalSourceOut,sizeof(SignalSourceOut));volatile Uint32emif16_ce_addr = 0x76000000;int count = sizeof(SignalSourceOut)/sizeof(int);for(i = 0; i < count; i++){int j = 0;*((unsigned short *)(emif16_ce_addr + 4 * 2 * i))= (unsigned short)tmp[i];*((unsigned short *)(emif16_ce_addr + 4 * (2 *i + 1)))= (unsigned short)(tmp[i] >> 16);for(j= 0; j<100; j++);}//free(tmp);unsigned int configChannel = 0;System_printf("Emif Setting... \n");signalSourceIn.jzControl= signalSourceIn.jzControl &0x1;signalSourceIn.modelSet= (signalSourceIn.modelSet&0x7)<<8;signalSourceIn.agcSet= (signalSourceIn.agcSet & 0x3f)<<16;configChannel = (signalSourceIn.modelSet|signalSourceIn.jzControl|signalSourceIn.agcSet);*((unsigned short *)(emif16_ce_addr + 104)) = (unsigned short)configChannel;*((unsigned short *)(emif16_ce_addr + 108)) = (unsigned short)(configChannel >> 16);System_printf("Emif Config Channel... \n");*((unsigned short *)(emif16_ce_addr + 128)) = 0;wait();*((unsigned short *)(emif16_ce_addr + 128)) = 1;wait();*((unsigned short *)(emif16_ce_addr + 128)) = 0;wait();System_printf("Emif Finished... \n");return;} void convertSignalSource(SignalSourceIn signalSourceIn,SignalSourceOut *signalSourceOut) {double user_freq, dds_freq;user_freq = signalSourceIn.dotFreq_frequence;dds_freq = 180*1000000;dac_source_dotfrq_config(user_freq, dds_freq,signalSourceOut);double fs, pri, pulsewidth, bandwidth, center_freq;fs = 180*1000000;pri = signalSourceIn.lfm_pri;pulsewidth = signalSourceIn.pulsewidth;bandwidth = signalSourceIn.bandwidth;center_freq = 0.0;unsigned intcpi_num, dwg_startpos, dwg_width;cpi_num = signalSourceIn.CPI;dwg_startpos = (unsigned int)(signalSourceIn.waveGateStart * fs);dwg_width = (unsigned int)(signalSourceIn.waveGateWidth);dac_source_lfm_config(fs, pri, pulsewidth, bandwidth, center_freq, cpi_num, dwg_startpos, dwg_width,signalSourceOut);target_config(signalSourceIn.targetSpeed, signalSourceIn.targetDistance, fs, 35.6e9 ,signalSourceOut);dac_source_config(signalSourceIn.dac_source_cfg,signalSourceOut); } Void setEmif(){signalSourceIn.CPI = 32;signalSourceIn.waveGateWidth = 2048.0;signalSourceIn.lfm_pri = 100e-6;setEmifValue(); } /////////////////////////////////////////////////////////////////////////////// EMIF16_CE_Config gNorCeCfg; /*the configuration for the CE of NOR FLASH*/ EMIF16_CE_Config gNandCeCfg;/*the configuration for the CE of NAND FLASH*/ EMIF16_Config gEmif16Cfg; void wait() {int i =0;for(i= 0; i<1000; i++); }void EMIF_init() {memset(&gNorCeCfg, 0, sizeof(gNorCeCfg));memset(&gNandCeCfg, 0, sizeof(gNandCeCfg));memset(&gEmif16Cfg, 0, sizeof(gEmif16Cfg));/*configuraiton for the CE of NOR FLASH*/gNorCeCfg.busWidth= EMIF_BUS_16BIT;gNorCeCfg.opMode= NOR_ASRAM_MODE;gNorCeCfg.strobeMode = SS_STROBE;gNorCeCfg.waitMode = EMIF_WAIT_NONE;gNorCeCfg.wrSetup = CSL_EMIF16_A0CR_WSETUP_RESETVAL;gNorCeCfg.wrStrobe = CSL_EMIF16_A0CR_WSTROBE_RESETVAL;gNorCeCfg.wrHold= CSL_EMIF16_A0CR_WHOLD_RESETVAL;gNorCeCfg.rdSetup= CSL_EMIF16_A0CR_RSETUP_RESETVAL;gNorCeCfg.rdStrobe= CSL_EMIF16_A0CR_RSTROBE_RESETVAL;gNorCeCfg.rdHold= CSL_EMIF16_A0CR_RHOLD_RESETVAL;gNorCeCfg.turnAroundCycles= CSL_EMIF16_A0CR_TA_RESETVAL;gNorCeCfg.nor_pg_Cfg= NULL;/*configuraiton for the CE of NAND FLASH*/gNandCeCfg.busWidth= EMIF_BUS_8BIT;gNandCeCfg.opMode= NAND_MODE;gNandCeCfg.strobeMode = SS_STROBE;gNandCeCfg.waitMode = EMIF_WAIT_NONE;/*timing configuration for NAND512R3A2DZA6E*/ #if 1gNandCeCfg.wrSetup = 1;//CSL_EMIF16_A0CR_WSETUP_RESETVAL,gNandCeCfg.wrStrobe = 4;//CSL_EMIF16_A0CR_WSTROBE_RESETVAL,gNandCeCfg.wrHold= 5;//CSL_EMIF16_A0CR_WHOLD_RESETVAL,gNandCeCfg.rdSetup= 1;//CSL_EMIF16_A0CR_RSETUP_RESETVALgNandCeCfg.rdStrobe= 7;//CSL_EMIF16_A0CR_RSTROBE_RESETVALgNandCeCfg.rdHold= 2;//CSL_EMIF16_A0CR_RHOLD_RESETVAL #elsegNandCeCfg.wrSetup = CSL_EMIF16_A0CR_WSETUP_RESETVAL;gNandCeCfg.wrStrobe = CSL_EMIF16_A0CR_WSTROBE_RESETVAL;gNandCeCfg.wrHold= CSL_EMIF16_A0CR_WHOLD_RESETVAL;gNandCeCfg.rdSetup= CSL_EMIF16_A0CR_RSETUP_RESETVAL;gNandCeCfg.rdStrobe= CSL_EMIF16_A0CR_RSTROBE_RESETVAL;gNandCeCfg.rdHold= CSL_EMIF16_A0CR_RHOLD_RESETVAL; #endifgNandCeCfg.turnAroundCycles= CSL_EMIF16_A0CR_TA_RESETVAL;gNandCeCfg.nor_pg_Cfg= NULL;#if NAND_FLASH_TESTgEmif16Cfg.ceCfg[0] = &gNandCeCfg; #elsegEmif16Cfg.ceCfg[0] = &gNorCeCfg;gEmif16Cfg.ceCfg[1] = &gNorCeCfg;gEmif16Cfg.ceCfg[2] = &gNorCeCfg;gEmif16Cfg.ceCfg[3] = &gNorCeCfg; #endifgEmif16Cfg.wait0Polarity= EMIF_LOW_WAIT;gEmif16Cfg.wait1Polarity= EMIF_LOW_WAIT;gEmif16Cfg.maxWait = CSL_EMIF16_AWCCR_MAXEXTWAIT_RESETVAL;KeyStone_EMIF16_init(&gEmif16Cfg);} /***@b Description*@n*Entry point for the example**@retval*Not Applicable.*/Void FxnZh(UArg arg0,UArg arg1){int tid; //omp_set_num_threads(8);while(1){System_printf("Fxn_zh has been excuted\n");#pragma omp parallel private(tid){tid=omp_get_thread_num();System_printf("core %d has activated\n",tid);}System_printf("Fxn_zh has join the main thread\n");System_printf("hang the FxnZh\n");Task_sleep(100);}}Void FxnEx(UArg arg0,UArg arg1){int tid;System_printf("FxnEx has been excuted!!!!\n"); } Void FxnEx2(UArg arg0,UArg arg1){int tid;System_printf("FxnEx2222222 has been excuted!!!!\n"); } Void main(Void) {Task_ParamstaskParams;Task_ParamstaskExParams;Task_ParamsMTDParams;int nthreads=8;/* Get the core number. */coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);EMIF_init();setEmif();/* Start the BIOS */BIOS_start(); }
user6224283：
回复 user6224283:
为了验证写了一个简短的omp程序FxnZh，cfg中一共启动3个task，主要的两个task函数名为FxnZh和dioExampleTask，FxnZh中周期性的在8个核心上输出，而dioExampleTask在core0上不断接受来自FPGA的中断，但是程序综合起来总是报INTERNAL ERROR: Unexpected NULL pointer – src/tomp_parallel.c, 224；此问题已经调试好长时间，希望Ti工程师们能给予解答，谢谢。
Shine：
回复 user6224283:
请试试下面帖子里的方法是否能解决“INTERNAL ERROR: Unexpected NULL pointer – src/tomp_parallel.c, 224”的报错信息。
www.51ele.net/forum.php
user6224283：
回复 Shine:
您好，非常感谢您的回复，这个我之前就试过了，不能解决我的问题，我还是比较怀疑qmss初始化有可能有问题，毕竟这两个task只是自己跑自己的是没有问题的，就是只有srio或者只有omp是没有问题的，只是sriotask一旦启动omp就会出现问题
user6224283：
回复 Shine:
还请您帮忙看一下问题出在哪，基本上能在网上找到的解决方案都已经找了
Shine：
回复 user6224283:
建议到e2e上咨询一下。
e2e.ti.com/…/791
user6224283：
回复 Shine:
您好请问之前没有srio和omp综合的例程吗，使用pdk2.0和omp2.0的
