TI中文支持网最近研究AM5728的PCIe，有些疑问没有搞明白，正好看到网上也有人问，就复制过来，看看TI的兄弟能不能帮忙解答一下。
I want to understand the usage of BARs in the PCIe Root Complex. The PCIe Root Complex is already a part of the CPU (as a peripheral to it). And the CPU register spaces is easily accessible. CPU has register to access its various peripheral link PCIe controller, DIMM Controller, USB Controllers etc. So in this case what is the usage of BAR inside the PCIe RC Config space ?
Secondly I want to understand how the PCIe RC is setup during enumeration with the proper memory windows. For example lets say I have a PCIe device (EP) directly connected to the RC. And in the Config space of EP programmed with some address 'X' with some size 's'. So basically, any read/write from the CPU to the window of 'X' and 'X +s', should go to the PCIe EP. But this should go through the PCIe RC. Now how the RC knows that it should it should translate the CPU read/write to that memory window into PCIe transaction to the EP ? How does the RC is configured to do that ? Are there any standardized register in PCIe RC where this information is kept ?
Jian Zhou：
请问这是从哪里复制过来的？
rtos：
回复 Jian Zhou:
具体地方忘记了，当时搜索root complex bar搜到的
最近看AM5728的PDK中关于PCIe的例子，由于对PCIe也是一知半解，那个程序看起来有很多地方和自己的理解不太一样，不知道有没有详细讲解例程的文档？
Jian Zhou：
回复 rtos:
请参考：
http://processors.wiki.ti.com/index.php/Processor_SDK_Linux_PCIe
rtos：
回复 Jian Zhou:
RTOS或裸跑环境下有没有完整的root complex例程？
Jian Zhou：
回复 rtos:
请先参考：
http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS_PCIe
