am335x ksz8895芯片 uboot ping不通

Hi,

  我们自己定制的板子，用的micrel的ksz8895芯片，现在的现象是uboot下ping不通。

U-Boot# mii info
PHY 0x01: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x02: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x03: OUI = 0x0885, Model = 0x05, Rev = 0x00, 100baseT, FDX
PHY 0x04: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x05: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x06: OUI = 0x0100, Model = 0x00, Rev = 0x04, 10baseT, HDX
PHY 0x07: OUI = 0x0180, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x0E: OUI = 0x0180, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x0F: OUI = 0x0100, Model = 0x00, Rev = 0x04, 10baseT, HDX
PHY 0x16: OUI = 0x2100, Model = 0x08, Rev = 0x00, 10baseT, HDX
PHY 0x17: OUI = 0x01C0, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x1E: OUI = 0x2200, Model = 0x08, Rev = 0x04, 10baseT, HDX
PHY 0x1F: OUI = 0x2200, Model = 0x08, Rev = 0x04, 10baseT, HDX

用mii命令查看到很多PHY，只有0x06地址可以正确读到phy芯片厂家信息

U-Boot# mdio read cpsw 6 0Reading from bus cpsw
PHY at address 6:
0 – 0x95

但是我们连接的是地址3

U-Boot# mdio list
cpsw:
3 – Micrel KSZ8895/KSZ8864 <–> cpsw

我已经移植了我们其他成熟设备的ksz8895驱动到uboot下。uboot打印信息如下

U-Boot 2014.10-dirty (Feb 26 2018 – 15:20:20)

Watchdog enabled
I2C: ready
DRAM: 512 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, total 8 MiB
*** Warning – bad CRC, using default environment

Net: phy_init
phy_init
phy_micrel_init
phy_micrel_init
ksz8895_write_smireg
ksz8895_write_smireg
ksz8895_config
ksz8895_config
cpsw, usb_ether
Hit any key to stop autoboot: 0

已经配置了#define CONFIG_PHY_MICREL

模式是RMII,这个我也已经设置了

writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RMII;

mux里面也做了修改

static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1},
};

configure_module_pin_mux(rmii1_pin_mux);

地址这里由0改为了3

static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 3,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};

不知道为题出在哪里，请帮忙看一下，多谢多谢。

Jian Zhou：

请问是哪个版本的SDK?

wei zhao：

回复 Jian Zhou:

您好，uboot是在uboot github上下载的，2014.10的版本。我们是参考BBB开发板的。

Jian Zhou：

回复 wei zhao:

搜一下这个函数cpsw_phy_init()，里面的 phy_connect()的参数是什么？

wei zhao：

回复 Jian Zhou:

phydev = phy_connect(priv->bus, slave->data->phy_addr, dev, slave->data->phy_if);

根据我们硬件工程师的确认，连接CPU的是PHY5，因此phy_addr我改成了5，还是不通。

static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 5, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 1, },};

Jian Zhou：

回复 wei zhao:

把slave->data->phy_addr这个参数直接改成5试试，如果MDIO无法和PHY芯片通信，请检查硬件。

user6237390：

回复 Jian Zhou:

Hi

请问这问题后来有解吗?我也遇到相同问题，KSZ设定成"SMI Interface Mode"

Thanks