TI中文支持网你好，我们在调试ths8200时遇到一些问题。
我们的hdmi和ths8200的输入是同源的；
vout输出1080p60时，
hdmi显示正常，如图1；
VGA正常显示为1920×1080/60HZ,但ths8200输出VGA的可视区域偏小，粗略估计横向左边少了240pixel如图2
我们ths8200的配置是TI官网下载的；
根据板子更改以下寄存器：
WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl – 20 bit input format 现为 0x50
WR_REG,THS8200,0x01,0x82,0x3B // pol_cntl, embed syncs enabled 现为 0x7b
调节WR_REG,THS8200,0x01,0x7A,0x7A // dtg_hs_in_dly_lsb – adjust horizontal 不能增加可视区域，但可以左右偏移
现在的问题是如何把那看不到的200多个pixel也都显示出来??
图1：
图2：
实际寄存器如下：
THS8200：
////////////////////////////////////////////////////////////////////////////////
BEGIN_DATASET // Appended by WinVCC4 v4.51. Saved all registers.
DATASET_NAME,"THS8200_1080p- 60Hz – 148.5 Mhz 20bit 422, Embedded Syncs, bt 601 range"
// THS8200WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl //CSC setup not required if not used WR_REG,THS8200,0x01,0x19,0x03 // csc_offset3 – CSC bypassedWR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl – 20 bit input format 0x50
// composite sync amplitude control
WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1 WR_REG,THS8200,0x01,0x1E,0x49 // dtg_y_sync2 WR_REG,THS8200,0x01,0x1F,0xB6 // dtg_y_sync3 WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1 WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2 WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3 WR_REG,THS8200,0x01,0x23,0x23 // dtg_y_sync_upper WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper// horizontal timing setupWR_REG,THS8200,0x01,0x25,0x2C // dtg_spec_a WR_REG,THS8200,0x01,0x26,0x58 // dtg_spec_b WR_REG,THS8200,0x01,0x27,0x2C // dtg_spec_c WR_REG,THS8200,0x01,0x28,0x84 // dtg_spec_d WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1 WR_REG,THS8200,0x01,0x2A,0xC0 // dtg_spec_e WR_REG,THS8200,0x01,0x2B,0x00 // dtg_spec_h_msb WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb WR_REG,THS8200,0x01,0x2F,0x58 // dtg_spec_k_lsb WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1 WR_REG,THS8200,0x01,0x32,0x58 // dtg_speg_g_lsb WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb WR_REG,THS8200,0x01,0x34,0x08 // dtg_total_pixel_msbWR_REG,THS8200,0x01,0x35,0x98 // dtg_total_pixel_lsbWR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb
WR_REG,THS8200,0x01,0x38,0x80 // dtg_mode – 1080p WR_REG,THS8200,0x01,0x39,0x44 // dtg_frame_field_msbWR_REG,THS8200,0x01,0x3A,0x65 // dtg_frame_size_lsb WR_REG,THS8200,0x01,0x3B,0x65 // dtg_field_size_lsb
WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode // discrete output sync control WR_REG,THS8200,0x01,0x70,0x2C // dtg_hlength_lsb WR_REG,THS8200,0x01,0x71,0x08 // dtg_hdly_msb WR_REG,THS8200,0x01,0x72,0x97 // dtg_hdly_lsb WR_REG,THS8200,0x01,0x73,0x06 // dtg_vlength_lsb WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb WR_REG,THS8200,0x01,0x77,0x00 // dtg_vdly2_msb WR_REG,THS8200,0x01,0x78,0x00 // dtg_vdly2_lsb // discrete input sync control – use to align picture WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb WR_REG,THS8200,0x01,0x7A,0x7A // dtg_hs_in_dly_lsb – adjust horizontal 0x0
WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb WR_REG,THS8200,0x01,0x7C,0x04 // dtg_vs_in_dly_lsb – adjust verticalWR_REG,THS8200,0x01,0x82,0x3B // pol_cntl, embed syncs enabled 0x7b
END_DATASET
//////////////////////////////////////////////////////////////////////////////////////////////////////
xing lixing：
调节WR_REG,THS8200,0x01,0x7A,0x7A // dtg_hs_in_dly_lsb – adjust horizontal 不能增加可视区域，但可以左右偏移，我的也有点左偏，大神这个寄存器是怎么算的，我如果设成7a更加的左偏，能否留下qq，谢谢可爱的大神
Eason Wang：
回复 xing lixing:
接显示器的时候，是否会在屏幕上打出来当前的分辨率？
xing lixing：
回复 Eason Wang:
不会在屏幕上打出来当前的分辨率，我用的1920×1080
