TI中文支持网技术文档中给出了以下描述：
The parallel interface complies with standard graphics interface protocol, which includes a vertical sync signal
(VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data
bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are
programmable. Figure 5 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is
optional in that the DLPC150 provides auto-framing parameters that can be programmed to define the data valid
window based on pixel and line counting relative to the horizontal and vertical syncs.
1.如果我使用MCU向DLPC150传输854*480个像素，时序图是怎样的呢？有没有传输几个像素的范例供参考呢？
2.parallel interface传输的每个像素之间，需要I2C总线进行配合吗？
谢谢解答。
Kevin Shi：
您好！
感谢关注TI的DLP产品。
1.请参考DLPC150数据手册6.11和6.12章节，有关于该接口的时序图。
http://www.ti.com/cn/lit/ds/symlink/dlpc150.pdf
2.在传输数据时不需要I2C总线配合。
谢谢
