关于TM4C1292NCPDT的timer PWM模式触发dma请求问题

你好：

我们想用TIMER的PWM模式触发DMA更新占空比，但是按datasheet配置完以后 ，中断处理程序一直接收到0x20 查看手册 意思是DMA传输已经完成，但是实际并没有更新，请帮忙看下吧。

datasheet 说明：

13.4.5 PWM Mode

A timer is configured to PWM mode using the following sequence:

1.

Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.

2.

Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.

3.

In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to

0x0, and the TnMR field to 0x2.

4.

Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field

of the GPTM Control (GPTMCTL) register.

5.

If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register

(GPTMTnPR).

6.

If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the

GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR

register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted

(see page 986).

7.

Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.

8.

Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.

9.

Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin

generation of the output PWM signal.

In PWM Time mode, the timer continues running after the PWM signal has been generated. The

PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes

effect at the next cycle after the write. 

代码：

uint16_t g_ui16RGBData[] = { 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95 };

void PerGenCfg(void)
{
//
// Enable the GPIO Peripheral.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
// Enable the Timer_1_A Peripheral.
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
ROM_GPIOPinConfigure(GPIO_PD2_T1CCP0);
ROM_GPIOPinTypeTimer(GPIO_PORTD_BASE, GPIO_PIN_2);
// Enable the uDMA Peripheral.
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
// Enable processor interrupts.
ROM_IntMasterEnable();
}

void ConfigureTimer1A(void)
{ // Disable Timer_1_A
ROM_TimerDisable(TIMER1_BASE, TIMER_A);
// Sets the clock source for the specified timer module.
TimerClockSourceSet(TIMER1_BASE, TIMER_CLOCK_SYSTEM);
// Configures the Timer_1_A.
//HWREG(TIMER1_BASE + TIMER_O_TAMR) = 0x20a;

ROM_TimerConfigure(TIMER1_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PWM);

// Sets the timer prescale value.
ROM_TimerPrescaleSet(TIMER1_BASE,TIMER_A, 0x00);
// Sets controls the output level.
ROM_TimerControlLevel(TIMER1_BASE, TIMER_A, false);
// Sets the timer load value and Match value.
ROM_TimerLoadSet(TIMER1_BASE, 150 – 1);
ROM_TimerMatchSet(TIMER1_BASE, 50 – 1);
// Enable PWM Mode interrupt.
HWREG(TIMER1_BASE + TIMER_O_TAMR) |= TIMER_TAMR_TAPWMIE;
ROM_uDMAEnable();
ROM_uDMAControlBaseSet(ui8ControlTable);
ROM_IntEnable(INT_UDMAERR);
ROM_uDMAChannelControlSet(UDMA_CH20_TIMER1A, UDMA_SIZE_16 | UDMA_DST_INC_NONE | UDMA_SRC_INC_16 | UDMA_ARB_1); ROM_uDMAChannelTransferSet(UDMA_CH20_TIMER1A | UDMA_PRI_SELECT, UDMA_MODE_AUTO, g_ui16RGBData ,
(void *)(TIMER1_BASE+TIMER_O_TBMATCHR), 256);
ROM_uDMAChannelAttributeDisable(UDMA_CH20_TIMER1A, UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST | UDMA_ATTR_REQMASK);
ROM_uDMAChannelAttributeEnable(UDMA_CH20_TIMER1A, UDMA_ATTR_HIGH_PRIORITY);
TimerDMAEventSet(TIMER1_BASE, TIMER_DMA_CAPEVENT_A);
TimerIntEnable(TIMER1_BASE, TIMER_TIMA_DMA);
TimerIntRegister(TIMER1_BASE, TIMER_A, Timer1IntHandler);

ROM_TimerEnable(TIMER1_BASE, TIMER_A);}