TI中文支持网#define RESULTS_BUFFER_SIZE 1024 // Buffer for storing conversion results
// (size must be multiple of 16)
#pragma DATA_SECTION(adcData0, "ramgs0");
#pragma DATA_SECTION(adcData1, "ramgs0");
Uint16 adcData0[RESULTS_BUFFER_SIZE];
Uint16 adcData1[RESULTS_BUFFER_SIZE];
DMAInitialize();
//
// DMA set up for first ADC
//
DMACH1AddrConfig(adcData0, &AdcaResultRegs.ADCRESULT0);
//
// Perform enough 16-word bursts to fill the results buffer. Data will be
// transferred 32 bits at a time hence the address steps below.
//
// Enable the DMA channel 1 interrupt
//
DMACH1BurstConfig(15, 2, 2);
DMACH1TransferConfig((RESULTS_BUFFER_SIZE >> 4) – 1, -14, 2);
DMACH1ModeConfig(
DMA_ADCAINT2,
PERINT_ENABLE,
ONESHOT_DISABLE,
CONT_DISABLE,
SYNC_DISABLE,
SYNC_SRC,
OVRFLOW_DISABLE,
THIRTYTWO_BIT,
CHINT_END,
CHINT_ENABLE
);
上例中的DMACH1TransferConfig((RESULTS_BUFFER_SIZE >> 4) – 1, -14, 2);几个参数如何理解？
Seven Han：// DMACH1TransferConfig –
//
void
DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{EALLOW;
//// Set up TRANSFER registers:////// Number of bursts per transfer, DMA interrupt will occur after // completed transfer//DmaRegs.CH1.TRANSFER_SIZE = tsize;//// TRANSFER_STEP is ignored when WRAP occurs//DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep;//// TRANSFER_STEP is ignored when WRAP occurs//DmaRegs.CH1.DST_TRANSFER_STEP = deststep;
EDIS;
}
配置每次触发DMA转移多少帧、帧间源地址增加偏移和帧间目的地址增加偏移。
请参考数据手册：www.ti.com/…/spruhx5e.pdf
