TI中文支持网近几天一直在看硬件i2c
在ti的launchpad的例程中 看到的i2c的示例代码中
主机接收
如这个代码
//******************************************************************************
// MSP430G2xx3 Demo – USCI_B0 I2C Master RX single bytes from MSP430 Slave
//
// Description: This demo connects two MSP430's via the I2C bus. The master
// reads from the slave. This is the master code. The data from the slave
// transmitter begins at 0 and increments with each transfer. The received
// data is in R5 and is checked for validity. If the received data is
// incorrect, the CPU is trapped and the P1.0 LED will stay on. The USCI_B0
// RX interrupt is used to know when new data has been received.
// ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.2MHz
//
// /|\ /|\
// MSP430G2xx3 10k 10k MSP430G2xx3
// slave | | master
// —————– | | —————–
// -|XIN P1.7/UCB0SDA|<-|—+->|P1.7/UCB0SDA XIN|-
// | | | | | 32kHz
// -|XOUT | | | XOUT|-
// | P1.6/UCB0SCL|<-+—–>|P1.6/UCB0SCL |
// | | | P1.0|–> LED
//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
#include "msp430g2553.h"
unsigned char RXData;
unsigned char RXCompare;
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1OUT &= ~BIT0; // P1.0 = 0
P1DIR |= BIT0; // P1.0 output
P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x048; // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
IE2 |= UCB0RXIE; // Enable RX interrupt
RXCompare = 0; // Used to check incoming data
while (1)
{
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTXSTT; // I2C start condition
while (UCB0CTL1 & UCTXSTT); // Start condition sent?
UCB0CTL1 |= UCTXSTP; // I2C stop condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
if (RXData != RXCompare) // Trap CPU if wrong
{
P1OUT |= BIT0; // P1.0 = 1
while (1); // Trap CPU
}
RXCompare++; // Increment correct RX value
}
}
// USCI_B0 Data ISR
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
RXData = UCB0RXBUF; // Get RX data
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
Peter_Zheng：
在user guide 第478页有I2C中断分配的详细说明。
In I2C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I2C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vect
EliteZhe：
回复 Peter_Zheng:
太感谢您了! 还有一个问题想请教一下,在c语言编程中(我看不太懂汇编….)
UCSTTIFG, UCSTPIFG, UCIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax 是对应 USCIAB0RX_VECTOR;
UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax是对应USCIAB0TX_VECTOR;
是吗?
EliteZhe：
回复 Peter_Zheng:
太感谢您了! 还有一个问题想请教一下,在c语言编程中(我看不太懂汇编….)
UCSTTIFG, UCSTPIFG, UCIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax 是对应 USCIAB0RX_VECTOR;
UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax是对应USCIAB0TX_VECTOR;
是吗?
Hardy Hu：
回复 EliteZhe:
应该是这样的，正解。
