TI中文支持网如何计算MSP430F5244 的IIC的UCB0BR0和UCB0BR1的值？
Maka Luo：
The I2C clock SCL is provided by the master on the I2C bus. When the USCI is in master mode, BITCLK isprovided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slavemode, the bit clock generator is not used and the UCSSELx bits are don't care.The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clocksource, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multi-mastermode, the maximum bit clock is fBRCLK/8. The BITCLK frequency is given by:fBitClock = fBRCLK/UCBRx
参见TI用户手册中说明
灰小子：
这款msp430各模块的配置方式都在手册里http://www.ti.com.cn/general/cn/docs/lit/getliterature.tsp?baseLiteratureNumber=slau208&fileType=pdf
