F2837xS_dma.h中关于CONTROL的定义:
struct CONTROL_BITS { // bits description
Uint16 RUN:1; // 0 Run Bit
Uint16 HALT:1; // 1 Halt Bit
Uint16 SOFTRESET:1; // 2 Soft Reset Bit
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit
Uint16 rsvd2:2; // 6:5 Reserved
Uint16 ERRCLR:1; // 7 Error Clear Bit
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit
Uint16 SYNCFLG:1; // 9 Sync Flag Bit
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit
Uint16 BURSTSTS:1; // 12 Burst Status Bit
Uint16 RUNSTS:1; // 13 Run Status Bit
Uint16 OVRFLG:1; // 14 Overflow Flag Bit
Uint16 rsvd1:1; // 15 Reserved
};
Susan Yang:以技术手册为准,您可以看一下 e2e.ti.com/…/572911
SYNC feature was specific to ADC and on F28379S we have new ADC which does not use this feature hence these fields are made reserved. No functional change to DMA architecture.