MSP430F5438A串口发送数据帧，一帧数据会被分开发送，中间的间隔达到惊人的16ms

在做MSP430F5438A的串口通讯的时候发送一帧数据，这帧数据很多时候会被分开发送，中间间隔多达16ms,请帮忙分析下是什么问题引起的，源代码如下：

#include "main.h"

#define P90_ON        (P9OUT |= BIT0)
#define P90_OFF        (P9OUT &=~BIT0)

unsigned char send_data[20]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x39,0x38,0x37,0x36,0x35,0x34,0x33,0x32,0x31,0x30};

//unsigned char send_data[2]={0,1};
unsigned char i=0;
int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;  //停止看门狗
  P9DIR |= BIT0;
  P90_OFF;
  System_Init();
//  _EINT();  
   while(1)
   {
      delay_ms(1000);
      if(i==0)
      {        P90_ON;
        UART3_SendStr(&send_data[0],20);        i++;
      }
      else if(i==1)
      {
        P90_OFF;
        UART3_SendStr(&send_data[0],20);        i=0;      
      }
   }
    
     
}

void delay_ms(int num)
{
  while(num–)
  __delay_cycles(20000);
}

void UART3_SendStr(unsigned char *dat,unsigned char k)
{
    while(k–)
    {
        UCA3TXBUF = *dat++;             // TX -> RXed character
        while (!(UCA3IFG&UCTXIFG));     // USCI_A0 TX buffer ready?
    }
}

#include "system.h"

void SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;              
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}

void UCS_Init(void)
{
    unsigned int N_FLL=0;
    UCSCTL3 |= SELREF_2;                      // Set DCO FLL reference = REFO  32768HZ
    UCSCTL4 |= SELA_3;                        // Set ACLK = REFO
    __bis_SR_register(SCG0);                  // Disable the FLL control loop
    UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_6;                      // Select DCO range 50MHz operation
    N_FLL = 609;//
    UCSCTL2 = FLLD_1 + N_FLL;                   // Set DCO Multiplier for 25MHz

    __bic_SR_register(SCG0);                  // Enable the FLL control loop
    __delay_cycles(781250);
 }

void UART_Init(void)
{
      P10SEL |= BIT4+BIT5;                       // P10.4,5 = USCI_A3 TXD/RXD  
      UCA3CTL1 |= UCSWRST;                      // **Put state machine in reset**
      UCA3CTL1 |= UCSSEL_2;                     // SMCLK +睡眠
      UCA3BR0 = 0xAD;                              // 20M 115200 (see User's Guide)2604
      UCA3BR1 = 0x00;                              // 20M 115200 (see User's Guide)
      UCA3MCTL |= UCBRS_2 + UCBRF_0;            // Modulation UCBRSx=1, UCBRFx=0
      UCA3CTL1 &= ~UCSWRST;      
      
}

void System_Init(void)
{

  SetVcoreUp(PMMCOREV_1);                     //12M
  SetVcoreUp(PMMCOREV_2);                     // Set VCore to 1.8MHz for 20MHz
  SetVcoreUp(PMMCOREV_3);                     //25M
  UCS_Init();
  UART_Init();
}

Loops：

你好。请用示波器查看是否有类似延时情况。 从程序看，没有问题。

user4682171：

回复 Loops:

示波器很难抓取到信号，毕竟通讯比较快，很难实时抓取到所要的信号，郁闷

user4682171：

回复 灰小子:

上位机的时间来源为接收到一帧数据后就实时获取的时间，跟缓冲区没有关系，跟延时显示也没有关系，因为时间不是屏幕刷新的时间，而是数据帧收到结束的时间

灰小子：

回复 user4682171:

用带存储的示波器，或者用逻辑分析仪，很容易抓到时序。
看看就知道原因了