TI中文支持网Part Number:WL1837MOD
Is Response and output data sampled during clock fall edge on default speed mode?
how to set sample edge to rise edge?
Alex Zhang：
您好，已经跟进您的问题
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Alex Zhang：
我相信这是您会在数据表中找到的信息：https://www.ti.com/lit/ds/symlink/wl1837mod.pdf
但我不确定你的目标是什么。你想完成什么？WL18x 和 Linux 主机上的 SDIO 驱动程序可以控制采样拓扑。它不可在 WL18x 上配置。
I believe this is information you will find in the datasheet: https://www.ti.com/lit/ds/symlink/wl1837mod.pdf
But I"m not sure what your goal is. What are you trying to accomplish? The SDIO driver on both the WL18x and the Linux Host has control over the sampling topology. It is not configurable on the WL18x.
