LMK04828: How to design LMK04828 nested zero-delay dual-loop Mode loop filter ？

Hollew specialist of TI:

  I encounter a troublesome，it is how to design LMK04828 nested zero-delay dual-loop Mode loop filter . I use LMK04828 designing nested zero-delay dual-loop Mode,

TI's Clock Design Tool software can design 2 separate PLL1 and PLL2,can not design nested zero-delay dual-loop Mode loop filter ，next picture is interface of Clock Design Tool software.

How to  design LMK04828 nested zero-delay dual-loop Mode loop filter is my encountered troublesome,

Amy Luo：

Hi Zhen,

To more effectively address your issue, I have consulted with TI senior engineers who have a better understanding of this IC. Once I receive a response, I will immediately reply to you.

,

Amy Luo：

For loop filter design of nested ZDM, you can design the filter as if the PLLs are cascaded. PLL2 noise contribution above PLL1 loop bandwidth is attenuated to negligible levels. Noise below PLL1 loop bandwidth is dominated by the CLKinX reference, the VCXO noise, and PLL1 FOM (combination of PFD frequency and charge pump gain), which are all the same in nested or cascaded configurations.