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求助——28035 PWM输出 时有时无

2012-06-06 分类：C2000™ 32位实时 MCU 阅读(258)

本人用tms320F28035做永磁同步电机控制，将Epwm1/2/3配置成互补的PWM输出，时钟同步上将ePWM1为主pwm，epwm2/3为从pwm。实验时出现奇怪的现象：有时候上电后，epwm1/2/3都能正常输出；有时候上电后，epwm1能够正常输出，epwm2/3没有输出（都是直接测量的DSP管脚）。请问，这可能是什么原因？

PWM配置代码如下：

//————————————————————-

//初始化Epwm1的寄存器

//————————————————————-

void InitEPwm1(void)

{

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   EDIS;

// Setup TBCLK

EPwm1Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

EPwm1Regs.TBCTL.bit.PHSDIR = 0;

EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm1Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;               // Up-dowm Counter mode

EPwm1Regs.TBCTL.bit.PHSEN = 0;                 // Master Module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;             // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm1Regs.TBCTL.bit.PRDLD = 0;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

// Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;

EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;  // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;  

// Set actions

EPwm1Regs.AQCTLA.bit.CAU = 0x2;                   // Set PWM1A High on event A, up count

   EPwm1Regs.AQCTLA.bit.CAD = 0x1;                   // Clear PWM1A Low on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = 0x1;

EPwm1Regs.AQCTLB.bit.CBD = 0x2;

   // ENABLE TRIG ADC

   EPwm1Regs.ETSEL.bit.SOCAEN = 1;                //

   EPwm1Regs.ETSEL.bit.SOCASEL = 1;               //

EPwm1Regs.ETPS.bit.SOCAPRD = 1;              

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

   EDIS;

}

//————————————————————-

//初始化Epwm2的寄存器

//————————————————————-

void InitEPwm2(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm2Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

EPwm2Regs.TBCTL.bit.PHSDIR = 1;

EPwm2Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm2Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm2Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm2Regs.TBCTL.bit.PRDLD = 0;

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm2Regs.AQCTLA.bit.CAU = 2;                   // Set PWM2A High on event A, up count

   EPwm2Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM2A Low on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = 1;

EPwm2Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm3的寄存器

//————————————————————-

void InitEPwm3(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm3Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

EPwm3Regs.TBCTL.bit.PHSDIR = 1;

EPwm3Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm3Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm3Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm3Regs.TBCTL.bit.PRDLD = 0;

EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm3Regs.AQCTLA.bit.CAU = 2;                   // Set PWM3A High on event A, up count

   EPwm3Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM3A Low on event A, down coun

EPwm3Regs.AQCTLB.bit.CBU = 1;

EPwm3Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm1中TripZone的寄存器

//————————————————————-

void InitTripZone(void)

{

EALLOW;

EPwm1Regs.TZSEL.bit.OSHT1 = 1;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;

EPwm3Regs.TZSEL.bit.OSHT1 = 1;

EPwm1Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM1A When oneshot Trip Event Occure

EPwm1Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM1B When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM2A When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM2B When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM3A When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM3B When oneshot Trip Event Occure

EPwm1Regs.TZEINT.bit.OST = 1;  //Enable interrupt EPWM1_TZINT

EDIS;

}

Jones Chen：

1. 楼主是否启用了TZ功能？是否因为外部异常导致PWM2和PWM3封波了？

2. 除了PWM2,3 以外，其他模块是否正常？

3. 请上电同时，用示波表检测三个TZ引脚，在不正常的输出情况下，应该有异常的低电平TZ信号输入。

本人用tms320F28035做永磁同步电机控制，将Epwm1/2/3配置成互补的PWM输出，时钟同步上将ePWM1为主pwm，epwm2/3为从pwm。实验时出现奇怪的现象：有时候上电后，epwm1/2/3都能正常输出；有时候上电后，epwm1能够正常输出，epwm2/3没有输出（都是直接测量的DSP管脚）。请问，这可能是什么原因？

PWM配置代码如下：

//————————————————————-

//初始化Epwm1的寄存器

//————————————————————-

void InitEPwm1(void)

{

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   EDIS;

// Setup TBCLK

EPwm1Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

EPwm1Regs.TBCTL.bit.PHSDIR = 0;

EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm1Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;               // Up-dowm Counter mode

EPwm1Regs.TBCTL.bit.PHSEN = 0;                 // Master Module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;             // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm1Regs.TBCTL.bit.PRDLD = 0;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

// Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;

EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;  // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;  

// Set actions

EPwm1Regs.AQCTLA.bit.CAU = 0x2;                   // Set PWM1A High on event A, up count

   EPwm1Regs.AQCTLA.bit.CAD = 0x1;                   // Clear PWM1A Low on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = 0x1;

EPwm1Regs.AQCTLB.bit.CBD = 0x2;

   // ENABLE TRIG ADC

   EPwm1Regs.ETSEL.bit.SOCAEN = 1;                //

   EPwm1Regs.ETSEL.bit.SOCASEL = 1;               //

EPwm1Regs.ETPS.bit.SOCAPRD = 1;              

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

   EDIS;

}

//————————————————————-

//初始化Epwm2的寄存器

//————————————————————-

void InitEPwm2(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm2Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

EPwm2Regs.TBCTL.bit.PHSDIR = 1;

EPwm2Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm2Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm2Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm2Regs.TBCTL.bit.PRDLD = 0;

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm2Regs.AQCTLA.bit.CAU = 2;                   // Set PWM2A High on event A, up count

   EPwm2Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM2A Low on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = 1;

EPwm2Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm3的寄存器

//————————————————————-

void InitEPwm3(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm3Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

EPwm3Regs.TBCTL.bit.PHSDIR = 1;

EPwm3Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm3Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm3Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm3Regs.TBCTL.bit.PRDLD = 0;

EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm3Regs.AQCTLA.bit.CAU = 2;                   // Set PWM3A High on event A, up count

   EPwm3Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM3A Low on event A, down coun

EPwm3Regs.AQCTLB.bit.CBU = 1;

EPwm3Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm1中TripZone的寄存器

//————————————————————-

void InitTripZone(void)

{

EALLOW;

EPwm1Regs.TZSEL.bit.OSHT1 = 1;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;

EPwm3Regs.TZSEL.bit.OSHT1 = 1;

EPwm1Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM1A When oneshot Trip Event Occure

EPwm1Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM1B When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM2A When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM2B When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM3A When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM3B When oneshot Trip Event Occure

EPwm1Regs.TZEINT.bit.OST = 1;  //Enable interrupt EPWM1_TZINT

EDIS;

}

Zhaobin Huang：

回复 Jones Chen:

陈生，你好！

我们只启用了TZ1功能，配置见代码中void InitTripZone(void)，其他的都没开。  用示波器测过T\Z\1\管脚电平，PWM输出不正常时T\Z\1\也是高电平。 另外，如果是进入T\Z\功能了，应该epwm1/2/3都不能正常输出才对，但现象是epwm1能正确输出pwm，其他却不能。

除pwm外，其他模块没有发现异常，spi/i2c等确定正常工作。

这个会不会跟pwm的EPwmxRegs.TBCTL.bit.SYNCOSEL配置有关？ 硬件设计上是不是有什么会影响到pwm的工作？

本人用tms320F28035做永磁同步电机控制，将Epwm1/2/3配置成互补的PWM输出，时钟同步上将ePWM1为主pwm，epwm2/3为从pwm。实验时出现奇怪的现象：有时候上电后，epwm1/2/3都能正常输出；有时候上电后，epwm1能够正常输出，epwm2/3没有输出（都是直接测量的DSP管脚）。请问，这可能是什么原因？

PWM配置代码如下：

//————————————————————-

//初始化Epwm1的寄存器

//————————————————————-

void InitEPwm1(void)

{

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   EDIS;

// Setup TBCLK

EPwm1Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

EPwm1Regs.TBCTL.bit.PHSDIR = 0;

EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm1Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;               // Up-dowm Counter mode

EPwm1Regs.TBCTL.bit.PHSEN = 0;                 // Master Module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;             // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm1Regs.TBCTL.bit.PRDLD = 0;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

// Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;

EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;  // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;  

// Set actions

EPwm1Regs.AQCTLA.bit.CAU = 0x2;                   // Set PWM1A High on event A, up count

   EPwm1Regs.AQCTLA.bit.CAD = 0x1;                   // Clear PWM1A Low on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = 0x1;

EPwm1Regs.AQCTLB.bit.CBD = 0x2;

   // ENABLE TRIG ADC

   EPwm1Regs.ETSEL.bit.SOCAEN = 1;                //

   EPwm1Regs.ETSEL.bit.SOCASEL = 1;               //

EPwm1Regs.ETPS.bit.SOCAPRD = 1;              

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

   EDIS;

}

//————————————————————-

//初始化Epwm2的寄存器

//————————————————————-

void InitEPwm2(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm2Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

EPwm2Regs.TBCTL.bit.PHSDIR = 1;

EPwm2Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm2Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm2Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm2Regs.TBCTL.bit.PRDLD = 0;

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm2Regs.AQCTLA.bit.CAU = 2;                   // Set PWM2A High on event A, up count

   EPwm2Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM2A Low on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = 1;

EPwm2Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm3的寄存器

//————————————————————-

void InitEPwm3(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm3Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

EPwm3Regs.TBCTL.bit.PHSDIR = 1;

EPwm3Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm3Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm3Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm3Regs.TBCTL.bit.PRDLD = 0;

EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm3Regs.AQCTLA.bit.CAU = 2;                   // Set PWM3A High on event A, up count

   EPwm3Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM3A Low on event A, down coun

EPwm3Regs.AQCTLB.bit.CBU = 1;

EPwm3Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm1中TripZone的寄存器

//————————————————————-

void InitTripZone(void)

{

EALLOW;

EPwm1Regs.TZSEL.bit.OSHT1 = 1;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;

EPwm3Regs.TZSEL.bit.OSHT1 = 1;

EPwm1Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM1A When oneshot Trip Event Occure

EPwm1Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM1B When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM2A When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM2B When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM3A When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM3B When oneshot Trip Event Occure

EPwm1Regs.TZEINT.bit.OST = 1;  //Enable interrupt EPWM1_TZINT

EDIS;

}

Jones Chen：

回复 Zhaobin Huang:

SYNC是同步功能，您使用了么？

如果使用了，必须是1的输出给2的输入，2的输出给3的输入。只有这一种顺序。

您在不正常的情况下，读取一下PWM2和PWM3的TB Counter，看看是否在变化。

本人用tms320F28035做永磁同步电机控制，将Epwm1/2/3配置成互补的PWM输出，时钟同步上将ePWM1为主pwm，epwm2/3为从pwm。实验时出现奇怪的现象：有时候上电后，epwm1/2/3都能正常输出；有时候上电后，epwm1能够正常输出，epwm2/3没有输出（都是直接测量的DSP管脚）。请问，这可能是什么原因？

PWM配置代码如下：

//————————————————————-

//初始化Epwm1的寄存器

//————————————————————-

void InitEPwm1(void)

{

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   EDIS;

// Setup TBCLK

EPwm1Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

EPwm1Regs.TBCTL.bit.PHSDIR = 0;

EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm1Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;               // Up-dowm Counter mode

EPwm1Regs.TBCTL.bit.PHSEN = 0;                 // Master Module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;             // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm1Regs.TBCTL.bit.PRDLD = 0;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

// Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;

EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;  // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;  

// Set actions

EPwm1Regs.AQCTLA.bit.CAU = 0x2;                   // Set PWM1A High on event A, up count

   EPwm1Regs.AQCTLA.bit.CAD = 0x1;                   // Clear PWM1A Low on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = 0x1;

EPwm1Regs.AQCTLB.bit.CBD = 0x2;

   // ENABLE TRIG ADC

   EPwm1Regs.ETSEL.bit.SOCAEN = 1;                //

   EPwm1Regs.ETSEL.bit.SOCASEL = 1;               //

EPwm1Regs.ETPS.bit.SOCAPRD = 1;              

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

   EDIS;

}

//————————————————————-

//初始化Epwm2的寄存器

//————————————————————-

void InitEPwm2(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm2Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

EPwm2Regs.TBCTL.bit.PHSDIR = 1;

EPwm2Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm2Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm2Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm2Regs.TBCTL.bit.PRDLD = 0;

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm2Regs.AQCTLA.bit.CAU = 2;                   // Set PWM2A High on event A, up count

   EPwm2Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM2A Low on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = 1;

EPwm2Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm3的寄存器

//————————————————————-

void InitEPwm3(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm3Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

EPwm3Regs.TBCTL.bit.PHSDIR = 1;

EPwm3Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm3Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm3Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm3Regs.TBCTL.bit.PRDLD = 0;

EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm3Regs.AQCTLA.bit.CAU = 2;                   // Set PWM3A High on event A, up count

   EPwm3Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM3A Low on event A, down coun

EPwm3Regs.AQCTLB.bit.CBU = 1;

EPwm3Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm1中TripZone的寄存器

//————————————————————-

void InitTripZone(void)

{

EALLOW;

EPwm1Regs.TZSEL.bit.OSHT1 = 1;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;

EPwm3Regs.TZSEL.bit.OSHT1 = 1;

EPwm1Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM1A When oneshot Trip Event Occure

EPwm1Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM1B When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM2A When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM2B When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM3A When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM3B When oneshot Trip Event Occure

EPwm1Regs.TZEINT.bit.OST = 1;  //Enable interrupt EPWM1_TZINT

EDIS;

}

Zhaobin Huang：

回复 Jones Chen:

谢谢陈生，我再看看寄存器TBCTR，确认下是否同步功能问题

本人用tms320F28035做永磁同步电机控制，将Epwm1/2/3配置成互补的PWM输出，时钟同步上将ePWM1为主pwm，epwm2/3为从pwm。实验时出现奇怪的现象：有时候上电后，epwm1/2/3都能正常输出；有时候上电后，epwm1能够正常输出，epwm2/3没有输出（都是直接测量的DSP管脚）。请问，这可能是什么原因？

PWM配置代码如下：

//————————————————————-

//初始化Epwm1的寄存器

//————————————————————-

void InitEPwm1(void)

{

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   EDIS;

// Setup TBCLK

EPwm1Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

EPwm1Regs.TBCTL.bit.PHSDIR = 0;

EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0

// Set Compare values

EPwm1Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm1Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;               // Up-dowm Counter mode

EPwm1Regs.TBCTL.bit.PHSEN = 0;                 // Master Module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0;             // Clock ratio to SYSCLKOUT

EPwm1Regs.TBCTL.bit.CLKDIV = 0x0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm1Regs.TBCTL.bit.PRDLD = 0;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;

// Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;

EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;  // Load on Zero

EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;  

// Set actions

EPwm1Regs.AQCTLA.bit.CAU = 0x2;                   // Set PWM1A High on event A, up count

   EPwm1Regs.AQCTLA.bit.CAD = 0x1;                   // Clear PWM1A Low on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = 0x1;

EPwm1Regs.AQCTLB.bit.CBD = 0x2;

   // ENABLE TRIG ADC

   EPwm1Regs.ETSEL.bit.SOCAEN = 1;                //

   EPwm1Regs.ETSEL.bit.SOCASEL = 1;               //

EPwm1Regs.ETPS.bit.SOCAPRD = 1;              

EALLOW;

   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

   EDIS;

}

//————————————————————-

//初始化Epwm2的寄存器

//————————————————————-

void InitEPwm2(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm2Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm2Regs.TBCTR = 0x0000;                      // Clear counter

EPwm2Regs.TBCTL.bit.PHSDIR = 1;

EPwm2Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm2Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm2Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm2Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm2Regs.TBCTL.bit.PRDLD = 0;

EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm2Regs.AQCTLA.bit.CAU = 2;                   // Set PWM2A High on event A, up count

   EPwm2Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM2A Low on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = 1;

EPwm2Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm3的寄存器

//————————————————————-

void InitEPwm3(void)

{

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;     // DISEnable TBCLK within the ePWM

EDIS;

// Setup TBCLK

EPwm3Regs.TBPRD = 3000;                      // Set timer period 801 TBCLKs

EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

EPwm3Regs.TBCTL.bit.PHSDIR = 1;

EPwm3Regs.TBPHS.half.TBPHS = 0x0002;           // Phase is 2

// Set Compare values

EPwm3Regs.CMPA.half.CMPA = 1500;     // Set compare A Init value

EPwm3Regs.CMPB = 1500;               // Set Compare B Init value

// Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = 2;               // Up-dowm Counter mode

EPwm3Regs.TBCTL.bit.PHSEN = 1;                 // Slave Module

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;             // Clock ratio to SYSCLKOUT

EPwm3Regs.TBCTL.bit.CLKDIV = 0;                //60MHZ/(1*1) = 60MHZ,EPWM模块始终频率为60MHZ

EPwm3Regs.TBCTL.bit.PRDLD = 0;

EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;

// Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;

EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;  // Load on Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;  

// Set actions

EPwm3Regs.AQCTLA.bit.CAU = 2;                   // Set PWM3A High on event A, up count

   EPwm3Regs.AQCTLA.bit.CAD = 1;                   // Clear PWM3A Low on event A, down coun

EPwm3Regs.AQCTLB.bit.CBU = 1;

EPwm3Regs.AQCTLB.bit.CBD = 2;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // DISEnable TBCLK within the ePWM

EDIS;

}

//————————————————————-

//初始化Epwm1中TripZone的寄存器

//————————————————————-

void InitTripZone(void)

{

EALLOW;

EPwm1Regs.TZSEL.bit.OSHT1 = 1;

EPwm2Regs.TZSEL.bit.OSHT1 = 1;

EPwm3Regs.TZSEL.bit.OSHT1 = 1;

EPwm1Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM1A When oneshot Trip Event Occure

EPwm1Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM1B When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM2A When oneshot Trip Event Occure

EPwm2Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM2B When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZA = 2;  //Pull down EPWM3A When oneshot Trip Event Occure

EPwm3Regs.TZCTL.bit.TZB = 2;  //Pull down EPWM3B When oneshot Trip Event Occure

EPwm1Regs.TZEINT.bit.OST = 1;  //Enable interrupt EPWM1_TZINT

EDIS;

}

Zhaobin Huang：

回复 Jones Chen:

测试了，pwm非正常输出时，寄存器TBCTR正常，三个都一样变化。 那还有什么原因可能导致这个问题呢？

电源质量会不会导致这个呢（如果+3.3V有所波动）？

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