TI中文支持网Part Number:LMK04828
The chip is configured in dual phase-locked loop mode, the clock output pin does not detect a clock signal, and the register configuration parameters are as follows
R0 (INIT) 0x000080
R0 0x000010
R2 0x000200
R3 0x000306
R4 0x0004D0
R5 0x00055B
R6 0x000600
R12 0x000C51
R13 0x000D04
R256 0x01000A
R257 0x010155
R258 0x010255
R259 0x010300
R260 0x010402
R261 0x010500
R262 0x0106F1
R263 0x010711
R264 0x01080A
R265 0x010955
R266 0x010A55
R267 0x010B00
R268 0x010C02
R269 0x010D00
R270 0x010EF9
R271 0x010F71
R272 0x011008
R273 0x011155
R274 0x011255
R275 0x011300
R276 0x011402
R277 0x011500
R278 0x0116F9
R279 0x011700
R280 0x011802
R281 0x011955
R282 0x011A55
R283 0x011B00
R284 0x011C02
R285 0x011D00
R286 0x011EF9
R287 0x011F33
R288 0x012008
R289 0x012155
R290 0x012255
R291 0x012300
R292 0x012402
R293 0x012500
R294 0x0126F9
R295 0x012700
R296 0x012808
R297 0x012955
R298 0x012A55
R299 0x012B00
R300 0x012C02
R301 0x012D00
R302 0x012EF9
R303 0x012F00
R304 0x01300A
R305 0x013155
R306 0x013255
R307 0x013300
R308 0x013402
R309 0x013500
R310 0x0136F1
R311 0x013751
R312 0x013800
R313 0x013900
R314 0x013A1F
R315 0x013BFF
R316 0x013C00
R317 0x013D08
R318 0x013E03
R319 0x013F00
R320 0x01400F
R321 0x014100
R322 0x014200
R323 0x014340
R324 0x014400
R325 0x01457F
R326 0x014600
R327 0x01471A
R328 0x01481B
R329 0x014913
R330 0x014A00
R331 0x014B16
R332 0x014C00
R333 0x014D00
R334 0x014EC0
R335 0x014F7F
R336 0x015003
R337 0x015102
R338 0x015200
R339 0x015300
R340 0x015401
R341 0x015500
R342 0x015604
R343 0x015700
R344 0x015804
R345 0x015900
R346 0x015A04
R347 0x015BD4
R348 0x015C20
R349 0x015D00
R350 0x015E00
R351 0x015F0B
R352 0x016000
R353 0x016104
R354 0x016244
R355 0x016300
R356 0x016400
R357 0x016501
R369 0x0171AA
R370 0x017202
R380 0x017C15
R381 0x017D33
R358 0x016604
R359 0x016700
R360 0x016832
R361 0x016959
R362 0x016A20
R363 0x016B00
R364 0x016C00
R365 0x016D03
R366 0x016E13
R371 0x017300
R386 0x018200
R387 0x018300
R388 0x018418
R389 0x018500
R392 0x018800
R393 0x018900
R394 0x018A00
R395 0x018B00
R8189 0x1FFD00
R8190 0x1FFE00
R8191 0x1FFF53
Amy Luo：
您好，
为更加有效地解决您的问题，我将您的问题发布在了E2E英文技术论坛上，请等待资深的英文论坛工程师为您提供帮助：
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1114509/lmk04828-no-output
,
Amy Luo：
E2E英文论坛工程师问，具体问题是什么？
您可以将您的输入是什么？您要实现什么？具体的问题表现是什么？或您的疑惑是什么等，具体描述下吗？
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?? ?：
Thank you for your reply. I've solved the problem mentioned earlier, it's my test device that's the problem. But I encountered a new problem, the auto mode in CLKin_SEL_MODE of LMK04828 PLL1 cannot be used. When the clkin0 signal source is disconnected, the chip does not automatically switch to CLKin1 to start working.The picture below is my configuration picture：
This is my specific register configuration
R0 (INIT) 0x000080 R0 0x000004 R2 0x000200 R3 0x000306 R4 0x0004D0 R5 0x00055B R6 0x000600 R12 0x000C51 R13 0x000D04 R256 0x01000A R257 0x010155 R258 0x010255 R259 0x010300 R260 0x010402 R261 0x010500 R262 0x010670 R263 0x010711 R264 0x01080A R265 0x010955 R266 0x010A55 R267 0x010BB1 R268 0x010C22 R269 0x010D00 R270 0x010E78 R271 0x010F11 R272 0x01100A R273 0x011155 R274 0x011255 R275 0x0113B1 R276 0x011422 R277 0x011500 R278 0x011678 R279 0x011733 R280 0x01180A R281 0x011955 R282 0x011A55 R283 0x011BB1 R284 0x011C22 R285 0x011D00 R286 0x011E79 R287 0x011F03 R288 0x012012 R289 0x012155 R290 0x012255 R291 0x0123B1 R292 0x012422 R293 0x012500 R294 0x012678 R295 0x012755 R296 0x012808 R297 0x012955 R298 0x012A55 R299 0x012B00 R300 0x012C02 R301 0x012D00 R302 0x012EF9 R303 0x012F00 R304 0x01300A R305 0x013155 R306 0x013255 R307 0x013300 R308 0x013402 R309 0x013500 R310 0x013670 R311 0x013711 R312 0x013800 R313 0x013903 R314 0x013A02 R315 0x013B80 R316 0x013C00 R317 0x013D0E R318 0x013E03 R319 0x013F04 R320 0x01400F R321 0x014100 R322 0x014200 R323 0x014321 R324 0x0144FF R325 0x01457F R326 0x014638 R327 0x01474A R328 0x01480B R329 0x01490B R330 0x014A02 R331 0x014B16 R332 0x014C00 R333 0x014D00 R334 0x014EC0 R335 0x014F7F R336 0x015003 R337 0x015102 R338 0x015200 R339 0x015300 R340 0x015401 R341 0x015500 R342 0x01560A R343 0x015700 R344 0x01580A R345 0x015900 R346 0x015A0A R347 0x015BD4 R348 0x015C20 R349 0x015D00 R350 0x015E00 R351 0x015F0B R352 0x016000 R353 0x016104 R354 0x016244 R355 0x016300 R356 0x016400 R357 0x016501 R369 0x0171AA R370 0x017202 R380 0x017C15 R381 0x017D33 R358 0x016600 R359 0x016700 R360 0x016832 R361 0x016959 R362 0x016A20 R363 0x016B00 R364 0x016C00 R365 0x016D00 R366 0x016E13 R371 0x017300 R386 0x018200 R387 0x018300 R388 0x018400 R389 0x018500 R392 0x018800 R393 0x018900 R394 0x018A00 R395 0x018B00 R8189 0x1FFD00 R8190 0x1FFE00 R8191 0x1FFF53
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Amy Luo：
很高兴您解决了帖子中的问题；
要在auto mode下使能输入时钟，CLKIN_SEL_MODE设置为–>4和LOS_EN –>1.
您设置的LOS_EN为0，似乎未使能auto mode。
请参照数据表中的9.3.5.3 部分，该部分有auto mode下时钟选择的顺序。
,
?? ?：
I have modified the register as you said, but still can't achieve the switch function
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Amy Luo：
I have fed your question back to the E2E engineer and when I get a response I will get back to you
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?? ?：
thanks
,
Amy Luo：
I haven't received a response so far, I've asked for progress and I'll be back here when I get any update
,
Amy Luo：
Sorry for the delay.
While doing the auto select CLKinx, device is not entering the holdover mode. Hence, seeing an unlock while changing the CLKinx or OFF the first CLKin.
To entering into the holdover mode, enable the HOLDOVER_PLL1_DET [1], which enters into the holdover mode, when PLL1 gets unlock.
Updated config file attached here FYR.
LMK04828_Auto_SEL_CLKinx.txt
R0 (INIT) 0x000090 R0 0x000004 R2 0x000200 R3 0x000306 R4 0x0004D0 R5 0x00055B R6 0x000600 R12 0x000C51 R13 0x000D04 R256 0x01000A R257 0x010155 R258 0x010255 R259 0x010300 R260 0x010402 R261 0x010500 R262 0x010670 R263 0x010711 R264 0x01080A R265 0x010955 R266 0x010A55 R267 0x010BB1 R268 0x010C22 R269 0x010D00 R270 0x010E78 R271 0x010F11 R272 0x01100A R273 0x011155 R274 0x011255 R275 0x0113B1 R276 0x011422 R277 0x011500 R278 0x011678 R279 0x011733 R280 0x01180A R281 0x011955 R282 0x011A55 R283 0x011BB1 R284 0x011C22 R285 0x011D00 R286 0x011E79 R287 0x011F03 R288 0x012012 R289 0x012155 R290 0x012255 R291 0x0123B1 R292 0x012422 R293 0x012500 R294 0x012678 R295 0x012755 R296 0x012808 R297 0x012955 R298 0x012A55 R299 0x012B00 R300 0x012C02 R301 0x012D00 R302 0x012EF9 R303 0x012F00 R304 0x01300A R305 0x013155 R306 0x013255 R307 0x013300 R308 0x013402 R309 0x013500 R310 0x013670 R311 0x013711 R312 0x013800 R313 0x013903 R314 0x013A02 R315 0x013B80 R316 0x013C00 R317 0x013D0E R318 0x013E03 R319 0x013F04 R320 0x01400F R321 0x014100 R322 0x014200 R323 0x014321 R324 0x0144FF R325 0x01457F R326 0x014618 R327 0x01474A R328 0x01480B R329 0x01490B R330 0x014A02 R331 0x014B16 R332 0x014C00 R333 0x014D00 R334 0x014EC0 R335 0x014F7F R336 0x015013 R337 0x015102 R338 0x015200 R339 0x015300 R340 0x015401 R341 0x015500 R342 0x01560A R343 0x015700 R344 0x01580A R345 0x015900 R346 0x015A0A R347 0x015BD4 R348 0x015C20 R349 0x015D00 R350 0x015E00 R351 0x015F0B R352 0x016000 R353 0x016104 R354 0x016244 R355 0x016300 R356 0x016400 R357 0x016532 R369 0x0171AA R370 0x017202 R380 0x017C15 R381 0x017D33 R358 0x016600 R359 0x016700 R360 0x016832 R361 0x016959 R362 0x016A20 R363 0x016B00 R364 0x016C00 R365 0x016D00 R366 0x016E13 R371 0x017300 R386 0x018200 R387 0x018300 R388 0x018400 R389 0x018500 R392 0x018800 R393 0x018900 R394 0x018A00 R395 0x018B00 R8189 0x1FFD00 R8190 0x1FFE00 R8191 0x1FFF53
