TI中文支持网Other Parts Discussed in Thread:OMAP-L138
你好，感谢能解决我的问题
C6746在做调试时，通过PLL0 OBSCLK输出管脚测试SYSCLKn时钟频率，写完程序后烧入bin文件后（bin文件下载至Norflash），发现DSP挂了。
之后想通过JTAG恢复，但是无法连接上，显示：
Error connecting to the target:
(Error -1143 @ 0x0)
Device core was hung. The debugger has forced the device to a ready state and recovered debug control, but your application's state is now corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further.
(Emulation package 5.0.747.0)
这里有2个问题：
1、根据datasheet配置，pll0regs->OCSEL = 0x17;pll0regs->OSCDIV = 0x8000 | 4;pll0regs->CKEN = 0x03;
这里的问题不知道出在哪里，是寄存器配置出错，还是时序的问题？
具体代码如下（新增代码加颜色）：
static void DEVICE_PLL0Init()
{
DEVICE_kickUnlock();
CSL_FINST(sys0regs->CFGCHIP0,SYSCFG_CFGCHIP0_PLL_MASTER_LOCK,FREE);//free PLL0
/*step 1: program CLKMODE bit in PLLCTL*/
if(CSL_FEXT(pll0regs->PLLCTL,PLLC_PLLCTL_PLLPWRDN))
{
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_CLKMODE,OSCIN);//use internal clock
}
/*step 2:switch pll to bypass mode
1.clear PLLENSRC bit in PLLCTL
2.select clock source by program EXTCLKSRC bit
3.clear PLLEN bit
4.wait 4 OSC cycles to ensure PLLC switched to bypass mode
*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLENSRC,CLEAR);
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_EXTCLKSRC,OSCIN);
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLEN,BYPASS);
// wait for 4 cycles to allow PLLEN mux switches properly to bypass clock
UTIL_waitLoopAccurate (4);
/*step 3: reset PLL by clear PLLRST bit*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLRST,ASSERT);//reset PLL
/*step 4: clear PLLPWRDN to 0*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLDIS,ASSERT);//disable PLL output
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLPWRDN,POWERED_UP);//power up PLL
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLDIS,DEASSERT);//enable PLL output
/*step 5: program multipler value in PLLM,and POSTDIV(OSCIN=25MHz)*/
CSL_FINS(pll0regs->PLLM,PLLC_PLLM_PLLM,23);//x24,SYSCLK=600MHz
CSL_FINS(pll0regs->POSTDIV,PLLC_POSTDIV_RATIO,1);//divide 2
/*step 6: program PLLnDIV for SYSCLKn
1.Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of PLL)
2.set RATIO for PLLnDIV
3.set GOSET in PLLCMD to 1
4.wait GOSTAT in PLLSTAT to 0(complete of divider)
*/
while(CSL_FEXT(pll0regs->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
CSL_FINS(pll0regs->PLLDIV2,PLLC_PLLDIV2_RATIO,1);//SYSCLK2=150MHz;
CSL_FINS(pll0regs->PLLDIV3,PLLC_PLLDIV3_RATIO,3);//SYSCLK3=75MHz;
CSL_FINS(pll0regs->PLLDIV4,PLLC_PLLDIV4_RATIO,3);//SYSCLK4=75MHz; //rjy_synclk_change mod,2->3
CSL_FINS(pll0regs->PLLDIV7,PLLC_PLLDIV7_RATIO,5);//SYSCLK7=50MHz,this can use for RMII clock;
pll0regs->OCSEL = 0x17;
pll0regs->OSCDIV = 0x8000 | 4;//div 5,(for test PLL clock)
/* Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. */
CSL_FINST(pll0regs->PLLCMD,PLLC_PLLCMD_GOSET,PHASE_ALIGN);
/* Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment). */
while(CSL_FEXT(pll0regs->PLLSTAT,PLLC_PLLSTAT_GOSTAT));
/*step 7:set PLLRST bit to 1(bring PLL out of RESET)*/
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLRST,DEASSERT);
/* Wait for PLL to lock. See PLL spec for PLL lock time */
UTIL_waitLoopAccurate (550);//2000*divide num/sqrt(multiple)
/* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode */
CSL_FINST(pll0regs->PLLCTL,PLLC_PLLCTL_PLLEN,PLL);
pll0regs->CKEN = 0x03;
CSL_FINST(sys0regs->CFGCHIP0,SYSCFG_CFGCHIP0_PLL_MASTER_LOCK,LOCK);//lock PLL0 DEVICE_kickLock();
}
2、如何恢复已经挂的芯片，使用方法
再次感谢！
Nancy Wang：
1、请问是配置没有生效吗？ccs中能否观察到寄存器值的改变？
2、芯片挂了是如何验证的？手动复位一下是否有用？如果将已烧写的程序先擦除，是否可以再次连接上？烧写的代码在线调试的时候是没有问题的吧？
,
user6622394：
您好，感谢你的答复。
1、CCS现在无法连接上仿真器，Device core was hung，应该是我写的程序，也就是上面添加绿色底的代码有问题，上电后norflash的程序被加载，导致dsp跑飞，影响了仿真器的连接
2、手动复位没用；
现在不知道如何才能擦除norflash，仿真器无法连接，请问有什么方法能重新连上仿真器？
,
Nancy Wang：
通过sfh_OMAP-L138.exe利用串口进行擦除。请下载：
sourceforge.net/…/
该工具的用法请参考2.2 Serial Boot and Flash Loading Utility
www.ti.com.cn/…/spracm8a.pdf
,
Shine：
试试把boot mode设成0001 1110 Emulation Debug模式。
,
user6622394：
boot mode相应的引脚做了更改，dsp不从norflash中加载程序，就可以正常连接上仿真器
,
Shine：
感谢分享！
