TI中文支持网Part Number:TDA3MV
各位好：
和大家请教下TDA3的问题。我之前设计的TDA3板回板了，这两天刚开始软硬件联调。过程中遇到些问题，想请教下。
使用CCS Debug，但上来就碰到个问题，Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)，字面意思应该是硬件错误。我复测了下复位，我的板子上仅使用了硬件上电复位，软复位引脚是拉高的。另外尝试把JTAG的TCK降频到1MHz，但还是报相同的问题。最后还是怀疑配置开关SYSBOOT15-0。附下log记录，有很多timeout的地方。
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence In Progress… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Cortex M4 Startup Sequence DONE! <<<—
ARP32_EVE_1: GEL Output: —>>> Configuring EVE Memory Map <<<—
ARP32_EVE_1: GEL Output: —>>> EVE Memory Map Done! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence Begins … <<<—
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: GEL Output: —>>> A device reset occurred <<<—
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C0: GEL Output: ==================================================
Cortex_M4_IPU1_C0: GEL Output: —>>> All Control module lock registers are UNLOCKED <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> Starting IPU A-MMU configurations… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> IPU A-MMU configuration completed. <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<—
Cortex_M4_IPU1_C0: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C0: GEL Output: —>>> 15×15 Package Detected(SYSBOOT[7]=0)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPPNOM in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 clock config in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Clock Configuration for OPP 0 is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules in progress… <<<—
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000C8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D0
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x000000D8
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C0: GEL Output: module_offset: 0x00000130
Cortex_M4_IPU1_C0: GEL Output: TIMEOUT
Cortex_M4_IPU1_C0: GEL Output: —>>> PRCM Configuration for all modules is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 initialization starts (TI 15×15 EVM)… <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 Initialization is in progress … <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in progress…
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C0: GEL Output: Launch full leveling
Cortex_M4_IPU1_C0: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C0: GEL Output: HW leveling is now disabled. Using slave ratios fromCortex_M4_IPU1_C0: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C0: GEL Output: —>>> DDR3 532MHz Initialization is DONE! <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx End All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C0: GEL Output: —>>> TDA3xx Target Connect Sequence DONE !!!!! <<<—
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: GEL Output: For STM based tracing on TI EVMs,Cortex_M4_IPU1_C0: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C0: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Target Connect Sequence Begins … <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> A device reset occurred <<<—
Cortex_M4_IPU1_C1: GEL Output: ==================================================
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C1: GEL Output: ==================================================
Cortex_M4_IPU1_C1: GEL Output: Core Reset has occurred.
Cortex_M4_IPU1_C1: GEL Output: ==================================================
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx PG3.0 device detected =========
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx GP Device detected ===========
Cortex_M4_IPU1_C1: GEL Output: ========= TDA3xx 15×15 Device detected ===========
Cortex_M4_IPU1_C1: GEL Output: ==================================================
Cortex_M4_IPU1_C1: GEL Output: —>>> All Control module lock registers are UNLOCKED <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> Changing RTI1 reaction type to avoid RTI1 resetting the device after 3 minutes… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> Starting IPU A-MMU configurations… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> IPU A-MMU configuration completed. <<<—
Cortex_M4_IPU1_C1: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR and DPLL configuration Based on Package selection pin status(Sysboot[7]) <<<—
Cortex_M4_IPU1_C1: GEL Output: ——————————————————————————————
Cortex_M4_IPU1_C1: GEL Output: —>>> 15×15 Package Detected(SYSBOOT[7]=0)… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> PRCM Clock Configuration for OPPNOM in progress… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> CORE DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C1: GEL Output: —>>> CORE DPLL OPP already locked, now unlocking….Cortex_M4_IPU1_C1: GEL Output: —>>> CORE DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: —>>> PER DPLL OPP 0 clock config in progress…
Cortex_M4_IPU1_C1: GEL Output: —>>> PER DPLL already locked, now unlockingCortex_M4_IPU1_C1: GEL Output: —>>> PER DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: —>>> DSP_GMAC DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C1: GEL Output: —>>> DSP_GMAC DPLL already locked, now unlocking….
Cortex_M4_IPU1_C1: GEL Output: —>>> DSP_GMAC DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: —>>> EVE_VID_DSP DPLL OPP 0 clock config is in progress…
Cortex_M4_IPU1_C1: GEL Output: —>>> DSP DPLL already locked, now unlocking….
Cortex_M4_IPU1_C1: GEL Output: —>>> EVE_VID_DSP_DPLL OPP 0 is DONE!
Cortex_M4_IPU1_C1: GEL Output: —>>> PRCM Clock Configuration for OPP 0 is DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> PRCM Configuration for all modules in progress… <<<—
Cortex_M4_IPU1_C1: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C1: GEL Output: module_offset: 0x000000C8
Cortex_M4_IPU1_C1: GEL Output: TIMEOUT
Cortex_M4_IPU1_C1: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C1: GEL Output: module_offset: 0x000000D0
Cortex_M4_IPU1_C1: GEL Output: TIMEOUT
Cortex_M4_IPU1_C1: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C1: GEL Output: module_offset: 0x000000D8
Cortex_M4_IPU1_C1: GEL Output: TIMEOUT
Cortex_M4_IPU1_C1: GEL Output: module_base: 0x4A009700
Cortex_M4_IPU1_C1: GEL Output: module_offset: 0x00000130
Cortex_M4_IPU1_C1: GEL Output: TIMEOUT
Cortex_M4_IPU1_C1: GEL Output: —>>> PRCM Configuration for all modules is DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR3 initialization starts (TI 15×15 EVM)… <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR3 Initialization is in progress … <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR DPLL clock config for 532MHz is in progress…
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR DPLL already locked, now unlocking….
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR DPLL clock config for 532MHz is in DONE!
Cortex_M4_IPU1_C1: GEL Output: Launch full leveling
Cortex_M4_IPU1_C1: GEL Output: Updating slave ratios in PHY_STATUSx registers
Cortex_M4_IPU1_C1: GEL Output: as per HW leveling output
Cortex_M4_IPU1_C1: GEL Output: HW leveling is now disabled. Using slave ratios fromCortex_M4_IPU1_C1: GEL Output: PHY_STATUSx registers
Cortex_M4_IPU1_C1: GEL Output: —>>> DDR3 532MHz Initialization is DONE! <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Begin All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Begin GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx End GMAC_SW MDIO Pad Configuration <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Begin GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx End GMAC_SW RGMII0 Pad Configuration <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx End All Pad Configuration for RGMII usage on EVM Platform <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx End All Pad Configuration for Vision Platform <<<—
Cortex_M4_IPU1_C1: GEL Output: —>>> TDA3xx Target Connect Sequence DONE !!!!! <<<—
Cortex_M4_IPU1_C1: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C1: GEL Output: For STM based tracing on TI EVMs,Cortex_M4_IPU1_C1: GEL Output: run 'TDA3x EVM I2C EXPANDER CONTROL -> Enable_Trace_Pins()' function from Scripts menu on M4/CS_DAP_DebugSS
Cortex_M4_IPU1_C1: GEL Output: !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Cortex_M4_IPU1_C1: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)。
如下图所示，目前我16个开关引脚 SYSBOOT15-SYSBOOT0从高到低配置为00111000 10000001，另外一个SW8001我硬件上没画（Debug模式下不影响）。按照这种配置，理论上来时SYSBOOT7应该是1，但我看log里面是“Cortex_M4_IPU1_C1: GEL Output: —>>> 15×15 Package Detected(SYSBOOT[7]=0)… <<<—”，想咨询下是否是SYSBOOT的影响从而导致报错呢？（本设计中，SYSBOOT7并未连接到开关上，而是直接连的QSPI FLASH）
期待回复，万分感谢！
Cherry Zhou：
您好我们已收到您的问题并升级到英文论坛，如有答复将尽快回复您。谢谢！
,
YYF：
再次感谢 期待你们的回复
,
Cherry Zhou：
抱歉回复晚了。
您所说的问题是在TI的板子上还是在您自己的板子上？
请问您为什么用CCS10？是与与旧版 CCS 配合使用的吗？
YYF 说：本设计中，SYSBOOT7并未连接到开关上，而是直接连的QSPI FLASH）
以及您能再解释下这个的含义吗？
,
YYF：
您好 我们调试使用的自己设计的板子 硬件架构基本同你们的开发板相同 只不过取消了GPMC（CPLD+NORFLASH）
CCS6.2 CCS9 CCS10以及最新的CCS11都使用过 现象都是一样的
最后SYSBOOT7引脚 是硬件上遗漏了 原来TDA3的R7管脚未引出至外部上下拉开关 已经通过飞线解决 但还是有如下问题
目前我们碰到的状况和论坛里面另外一位工程师很类似 使用XDS110以及Blackhawk 560 V2连接JTAG test connection可以成功 且能扫到TDA3的5个内核 但我们使用CCS的example库 打印“hello world” 就会报“Cortex_M4_IPU1_C1: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.4.0.00006) ”错误
这两天使用了开发板的SDK 但还是会报“a data verification error occured，file load failed”错误。
硬件上也复查过 上电时序目前为1.8V 1.35V 1.06VCORE 1.06VDSPEVE 3.3V 然后使能20M时钟 最后拉高POR 以上波形均使用示波器点测过 应该没有问题
还希望你们再帮忙看下 提供些思路 谢谢
,
Cherry Zhou：
dear，一般情况下是没有办法只从CSS构建和运行一些example的，memory map可能和板子上可用map不匹配。
数据验证错误表示您尝试加载的程序被放置到无效的存储器区域。通常是您example的连接器命令文件的问题。
,
YYF：
谢谢 我们先根据Emif tools查一下ddr的问题
