TI中文支持网Part Number:TMS320F28379D
ADC差分16位采样450Khz信号，在不启动硬件加速器情况下采样正常，启动后出现采样个别值偏离范围，代码如下：
void ConfigureADC(void)
{
EALLOW;
// clock configuration
AdcaRegs.ADCCTL2.bit.PRESCALE = 3; // set ADCCLK divider to /2.5 3
AdcbRegs.ADCCTL2.bit.PRESCALE = 3; // set ADCCLK divider to /2.5 3
AdccRegs.ADCCTL2.bit.PRESCALE = 3; // set ADCCLK divider to /2.5 3
AdcdRegs.ADCCTL2.bit.PRESCALE = 3; // set ADCCLK divider to /3 4
// resolution and signal model configuration
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_16BIT, ADC_SIGNALMODE_DIFFERENTIAL);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
// Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt occurs after converter finish
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt occurs after converter finish
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt occurs after converter finish
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Interrupt occurs after converter finish
// power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
// delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
}
void SetupADCContinuous(Uint16 channel_a, Uint16 channel_b, Uint16 channel_c)
{
Uint16 acqps_16;
Uint16 acqps_12;
acqps_16 = 10; // 3+1=4; 4*5=20ns
acqps_12 = 3; // 3+1=4; 4*5=20ns
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC1CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC2CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC3CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC4CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC5CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC6CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC7CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC8CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC9CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC10CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC11CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC12CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC13CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC14CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC15CTL.bit.CHSEL = channel_a; // SOC will convert on channel
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC8CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC9CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC10CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC11CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC12CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC13CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC14CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcaRegs.ADCSOC15CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
EDIS;
EALLOW;
AdcbRegs.ADCSOC0CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC1CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC2CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC3CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC4CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC5CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC6CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC7CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC8CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC9CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC10CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC11CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC12CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC13CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC14CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC15CTL.bit.CHSEL = channel_b; // SOC will convert on channel
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC4CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC5CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC6CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC7CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC8CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC9CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC10CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC11CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC12CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC13CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC14CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdcbRegs.ADCSOC15CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
// AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 3; //end of SOC3 will Start CLA5(ADC0-ADC3)
// AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 7; //end of SOC7 will Start CLA6(ADC4-ADC7),It also will check ADCA,ADCB the same time
// AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 12; //end of SOC12 will Start CLA7(ADC9-ADC12)
// AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 15; //end of SOC15 will Start CLA8(ADC13-ADC15)
EDIS;
EALLOW;
AdccRegs.ADCSOC0CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC1CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC2CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC3CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC4CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC5CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC6CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC7CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC8CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC9CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC10CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC11CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC12CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC13CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC14CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC15CTL.bit.CHSEL = channel_c; // SOC will convert on channel
AdccRegs.ADCSOC0CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC2CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC3CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC4CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC5CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC6CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC7CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC8CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC9CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC10CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC11CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC12CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC13CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC14CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
AdccRegs.ADCSOC15CTL.bit.ACQPS = acqps_16; // sample window is acqps + 1 SYSCLK cycles
EDIS;
EALLOW;
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC1CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC2CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC3CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC4CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC5CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC6CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC7CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC8CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC9CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC10CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC11CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC12CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC13CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC14CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC15CTL.bit.CHSEL = 12; // SOC will convert on channel
AdcdRegs.ADCSOC0CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC1CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC2CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC3CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC4CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC5CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC6CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC7CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC8CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC9CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC10CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC11CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC12CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC13CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC14CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
AdcdRegs.ADCSOC15CTL.bit.ACQPS = acqps_12; // sample window is acqps + 1 SYSCLK cycles
EDIS;
}
SetupADCContinuous(2,2,2); // ADCA_A2-A3. ADCB_B2-B3. ADCC_C2-C3. DIFFERENTIAL SIGNAL
// ADCD D0,D1,D4. SINGLE SIGNAL
// ……………………….Setup the ADC as BURST MODE…………………………//
EALLOW;
AdcaRegs.ADCINTFLGCLR.all = 0x000F; // The interrupt flag is cleared
AdcbRegs.ADCINTFLGCLR.all = 0x000F; // The interrupt flag is cleared
AdccRegs.ADCINTFLGCLR.all = 0x000F; // The interrupt flag is cleared
AdcdRegs.ADCINTFLGCLR.all = 0x000F; // The interrupt flag is cleared
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1; // ENABLE BURSTCTL MODE
AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1; // ENABLE BURSTCTL MODE
AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1; // ENABLE BURSTCTL MODE
AdcdRegs.ADCBURSTCTL.bit.BURSTEN = 1; // ENABLE BURSTCTL MODE
AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 0x9; // EPWM3.ADCSOCA AS A TRIGER SOURCE
AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 0x9; // EPWM3.ADCSOCA AS A TRIGER SOURCE
AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 0x9; // EPWM3.ADCSOCA AS A TRIGER SOURCE
AdcdRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 0x9; // EPWM3.ADCSOCA AS A TRIGER SOURCE
AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 0; // EVERY TRIGER START 1 EOC
AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 0; // EVERY TRIGER START 1 EOC
AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 0; // EVERY TRIGER START 1 EOC
AdcdRegs.ADCBURSTCTL.bit.BURSTSIZE = 1; // EVERY TRIGER START 2 EOC : ADCD0,ADCD1;
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 1; // SETTING TRIGER PIRIOR
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 7; // AdcaINT1 triggers two cpu's CLA to calculate EOC0-SOC7. The trigger is at Adca.soc7.
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 15; // AdcaINT2 triggers two cpu's CLA to calculate EOC8-SOC15. The trigger is at Adca.soc15.
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // ENABLE AdcINT1
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; // ENABLE AdcINT2
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Ignore FLAG CLEAN
AdcaRegs.ADCINTSEL1N2.bit.INT2CONT = 1; // Ignore FLAG CLEAN
Green Deng：
你好，请问你说的硬件加速器是指什么硬件加速器？是C2000自带的运算模块硬件加速器吗？
,
user6122765：
运算模块硬件加速器
,
Green Deng：
方便说明一下具体是怎么样的偏差？另外，测试是在ram环境下还是flash环境下测试的？
目前来说还没有涉及硬件加速器影响ADC采样的情况，有没有跟测试环境条件或者其他因素有关？
,
user6122765：
问题解决了，降低ADCCLK频率。
