TI中文支持网问题找到了，就是将0x3F8000的L0当作一个内存来用，其实他和0x008000的内存是同一个内存~~~~
请无视此贴……
问题比较复杂，一步一步说：
F28035芯片，CCS5.5，实验设备有TI原装的DRV8412-C2-KIT，原来参照controlSuite的例子 《development_kits\TMDSIACLEDCOMKIT_v1.1\IsoACLighting-F28027-DMX512 》 将SCI中断服务函数放到RAM内存中运行，一切正常。不过CMD文件是用另一个例子《development_kits\DRV8412-C2-KIT_v131\GUI_project 》 中的 “F28035_FLASH_DRV8412GUI.CMD”。
后来由于自己的程序需要使用CLA，并且使用了CLAmath.Lib，参阅了例子 《 development_kits\HVMotorCtrl+PfcKit_v2.1\HVPM_Sensorless_CLA_F2803x 》，最后整合出来新的CMD文件（另见附件）。
现在问题来了，首先，如果SCI的中断服务程序还是拷贝到RAM中的话，一进入中断就出错，出错表现为跳到例程中的”interrupt void ISR_ILLEGAL(void)“函数中。如果注释掉 #pragma CODE_SECTION (sciaRxIsr, "ramfuncs") 这个语句，就能正常运行。
还有一个问题，在仿真模式下，CLA 和 CLAmath函数都能正常运行，但是，如果断电后再启动芯片，CLA就出错了。通过主CPU的中断函数输出，可以判断CLA还是在运行的。重新在CCS中连接上芯片后，观察CLA中的变量，发现出错的是CLAmath的函数CLAsinPU。
所以综合前面那个SCI中断函数的问题，感觉就是，可能CMD文件和相关的代码没处理好，现在只要是运行时要拷贝到Ram内存的东西，除了CLA 拷贝到 progRam没问题外，其他的都有问题。
实在研究不出来，请求专家帮忙看看。
参照例程，CLA的拷贝函数是
memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);
SCI的拷贝函数是
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
编译时没有任何错误，最原始的工程项目是development_kits\DRV8412-C2-KIT_v131\GUI_project 。
user4362943：
回复 HH Y:
你好，大神，现在用TMS320F28027芯片，由于程序比较大，0x008000-0x009000 这个空间不够用，能不能把一部分程序放到0x3f8000-0x3f9000中呢？非常感谢
HH Y：
回复 user4362943:
程序放到哪里都可以，只是一些比较特殊的，如Flash擦写，CLA，就一定要放到RAM中，或者追求运行速度快的，也应该放到RAM中。我的问题的根源，是芯片上同一块区域，起了两个名字，我没留意，另一个问题是没有把CLA用到的数据拷贝到对应的RAM中。027我不熟，不过我知道027没有CLA，只要确认那个地址范围是存在的，且没有和其他地址范围共同指向同一片区域，就可以放心使用。
user1937915：
回复 HH Y:
大神我遇到了你第一个问题，就是有部分代码需要在RAM中运行，同时也添加了CLA模块。也是出现CLA正常，但是一旦程序运行xxxx函数（#pragma CODE_SECTION (xxxx, "ramfuncs")）了。程序就会跑入到interrupt void ISR_ILLEGAL(void)“函数中。我排查了下我自己的CMD文件，没有发现有同一个内存，分配了2个不同名字的情况。大神知道还有什么可能原因会导致这个现象不？
user1937915：
回复 HH Y:
下面是我的CMD文件：
/*
//###########################################################################
//
// FILE:F28035_CLA_C.cmd
//
// TITLE: Linker Command File For F28035 Device
//
//###########################################################################
// $TI Release: F2803x C/C++ Header Files and Peripheral Examples V130 $
// $Release Date: May8, 2015 $
// $Copyright: Copyright (C) 2009-2015 Texas Instruments Incorporated –
//http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*//* ======================================================
// For Code Composer Studio V2.2 and later
// —————————————
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2803x_Headers\cmd
//
// For BIOS applications add:DSP2803x_Headers_BIOS.cmd
// For nonBIOS applications add:DSP2803x_Headers_nonBIOS.cmd
========================================================= *//* ======================================================
// For Code Composer Studio prior to V2.2
// ————————————–
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map*//* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2803x_Headers_nonBIOS.cmd *//* Uncomment this line to include file only for BIOS applications */
/* -l DSP2803x_Headers_BIOS.cmd *//* 2) In your project add the path to <base>\DSP2803x_headers\cmd to thelibrary search path under project->build options, linker tab,library search path (-i).
/*========================================================= *//* Define the memory block start/length for the F28035PAGE 0 will be used to organize program sectionsPAGE 1 will be used to organize data sections
Notes:Memory blocks on F2803x are uniform (ie samephysical memory) in both PAGE 0 and PAGE 1.That is the same memory region should not bedefined for both PAGE 0 and PAGE 1.Doing so will result in corruption of programand/or data.
L0 memory block is mirrored – that isit can be accessed in high memory or low memory.For simplicity only one instance is used in thislinker file.
Contiguous SARAM memory blocks or flash sectors can bebe combined if required to create a larger memory block.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x300
-stack 0x300// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
// CLA_SCRATCHPAD_SIZE = 0x100;
–undef_sym=__cla_scratchpad_end
–undef_sym=__cla_scratchpad_startMEMORY
{
PAGE 0:/* Program Memory *//* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */RAML0: origin = 0x009000, length = 0x000800/* on-chip RAM block L3 */RAML1: origin = 0x009800, length = 0x000800/* on-chip RAM block L4 */OTP: origin = 0x3D7800, length = 0x000400/* on-chip OTP */
//FLASHH: origin = 0x3E8000, length = 0x002000/* on-chip FLASH */
//FLASHG: origin = 0x3EA000, length = 0x002000/* on-chip FLASH */FLASHF: origin = 0x3E8000, length = 0x002000/* on-chip FLASH */FLASHE: origin = 0x3EA000, length = 0x002000/* on-chip FLASH */FLASHD: origin = 0x3EC000, length = 0x002000/* on-chip FLASH */FLASHC: origin = 0x3EE000, length = 0x006000/* on-chip FLASH */FLASHA: origin = 0x3F6000, length = 0x001F80/* on-chip FLASH */CSM_RSVD: origin = 0x3F7F80, length = 0x000076/* Part of FLASHA.Program with all 0x0000 when CSM is in use. */BEGIN: origin = 0x3F7FF6, length = 0x000002/* Part of FLASHA.Used for "boot to Flash" bootloader mode. */CSM_PWL_P0: origin = 0x3F7FF8, length = 0x000008/* Part of FLASHA.CSM password locations in FLASHA */
IQTABLES: origin = 0x3FE000, length = 0x000B50/* IQ Math Tables in Boot ROM */IQTABLES2: origin = 0x3FEB50, length = 0x00008C/* IQ Math Tables in Boot ROM */IQTABLES3: origin = 0x3FEBDC, length = 0x0000AA/* IQ Math Tables in Boot ROM */
ROM: origin = 0x3FF27C, length = 0x000D44/* Boot ROM */RESET: origin = 0x3FFFC0, length = 0x000002/* part of boot ROM*/VECTORS: origin = 0x3FFFC2, length = 0x00003E/* part of boot ROM*/PAGE 1 :/* Data Memory *//* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation *//* Registers remain on PAGE1*/BOOT_RSVD: origin = 0x000000, length = 0x000050/* Part of M0, BOOT rom will use this for stack */RAMM0: origin = 0x000050, length = 0x0000B0/* on-chip RAM block M0 */RAMM1: origin = 0x000100, length = 0x000400/* on-chip RAM block M1 */RAML2: origin = 0x008000, length = 0x000800/* on-chip RAM block L0 */CLARAM0: origin = 0x008800, length = 0x000400CLARAM1: origin = 0x008C00, length = 0x000400CLA1_MSGRAMLOW: origin = 0x001480, length = 0x000080CLA1_MSGRAMHIGH: origin = 0x001500, length = 0x000080FLASHB: origin = 0x3F4000, length = 0x002000/* on-chip FLASH */
}
/* Allocate sections to memory blocks.Note:codestart user defined section in DSP28_CodeStartBranch.asm used to redirect codeexecution when booting to flashramfuncsuser defined section to store functions that will be copied from Flash into RAM
*/SECTIONS
{
/* Allocate program areas: */.cinit: > FLASHAPAGE = 0.pinit: > FLASHA,PAGE = 0.text: > FLASHCPAGE = 0codestart: > BEGINPAGE = 0ramfuncs: LOAD = FLASHD,RUN = RAML1,/*LOAD_START(_RamfuncsLoadStart),//LOAD_END(_RamfuncsLoadEnd),LOAD_SIZE(_RamfuncsLoadSize),RUN_START(_RamfuncsRunStart),*/LOAD_START(_RamfuncsLoadStart),LOAD_END(_RamfuncsLoadEnd),RUN_START(_RamfuncsRunStart),LOAD_SIZE(_RamfuncsLoadSize),PAGE = 0csmpasswds: > CSM_PWL_P0PAGE = 0csm_rsvd: > CSM_RSVDPAGE = 0/* Allocate uninitalized data sections: */.stack: > RAMM1PAGE = 1.cio: >> RAML2 | RAMM1PAGE = 1.sysmem: > RAMM1PAGE = 1.ebss: > RAML2PAGE = 1.esysmem: > RAML2PAGE = 1/* Initalized sections go in Flash *//* For SDFlash to program these, they must be allocated to page 0 */.econst: > FLASHAPAGE = 0.switch: > FLASHAPAGE = 0/* Allocate IQ math areas: */IQmath: > FLASHAPAGE = 0/* Math Code */IQmathTables: > IQTABLES,PAGE = 0, TYPE = NOLOAD.bss_cla: > CLARAM0,PAGE = 1.scratchpad: > CLARAM0,PAGE = 1Cla1Prog: LOAD = FLASHD,RUN = RAML0,LOAD_START(_Cla1funcsLoadStart),LOAD_END(_Cla1funcsLoadEnd),RUN_START(_Cla1funcsRunStart),LOAD_SIZE(_Cla1funcsLoadSize),PAGE = 0Cla1ToCpuMsgRAM: > CLA1_MSGRAMLOW,PAGE = 1CpuToCla1MsgRAM: > CLA1_MSGRAMHIGH,PAGE = 1Cla1DataRam0: > CLARAM0,PAGE = 1Cla1DataRam1: > CLARAM1,PAGE = 1GROUP: LOAD = FLASHB,RUN = CLARAM1,LOAD_START(_Cla1mathTablesLoadStart),LOAD_END(_Cla1mathTablesLoadEnd),RUN_START(_Cla1mathTablesRunStart),LOAD_SIZE(_Cla1mathTablesLoadSize),PAGE = 1{CLA1mathTables.const_cla}CLAscratch: { *.obj(CLAscratch). += CLA_SCRATCHPAD_SIZE;*.obj(CLAscratch_end) } > CLARAM0,PAGE = 1/* Uncomment the section below if calling the IQNexp() or IQexp()functions from the IQMath.lib library in order to utilize therelevant IQ Math table in Boot ROM (This saves space and Boot ROMis 1 wait-state). If this section is not uncommented, IQmathTables2will be loaded into other memory (SARAM, Flash, etc.) and will takeup space, but 0 wait-state is possible.*//*IQmathTables2: > IQTABLES2, PAGE = 0, TYPE = NOLOAD{IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)}*//* Uncomment the section below if calling the IQNasin() or IQasin()functions from the IQMath.lib library in order to utilize therelevant IQ Math table in Boot ROM (This saves space and Boot ROMis 1 wait-state). If this section is not uncommented, IQmathTables2will be loaded into other memory (SARAM, Flash, etc.) and will takeup space, but 0 wait-state is possible.*//*IQmathTables3: > IQTABLES3, PAGE = 0, TYPE = NOLOAD{IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)}*/
/* .reset is a standard section used by the compiler.It contains the *//* the address of the start of _c_int00 for C Code./*/* When using the boot ROM this section and the CPU vector *//* table is not needed.Thus the default type is set here to*//* DSECT*/.reset: > RESET,PAGE = 0, TYPE = DSECTvectors: > VECTORSPAGE = 0, TYPE = DSECT}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
