TI中文支持网专家：你好，我这有一段如下发波程序：
//PWM1的配置
EALLOW;
// TB
EPwm1Regs.TBPRD = 300;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
//CC
EPwm1Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty for EPWM1A
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
//AQ
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//DB
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A is the source for both delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBFED = 18; // FED = 10 TBCLKs initially
EPwm1Regs.DBRED = 18; // RED = 10 TBCLKs initially
//ET
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
//PWM2的配置
// TB
EPwm2Regs.TBPRD = 300;
EPwm2Regs.TBPHS.half.TBPHS = 75; // Set Phase register to PWM_PRD_USE_MIN/4 initially
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
//CC
EPwm2Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty EPWM2A
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
//AQ
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//DB
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWM1A is the source for both delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBFED = 18; // FED = 10 TBCLKs initially
EPwm2Regs.DBRED = 18; // RED = 10 TBCLKs initially
//ET
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EDIS;
这段程序的本意是配置EPWM1与EPWM2相位相差90°，当我使能EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm2Regs.TBPHS.half.TBPHS = 75; EPWM1发波正常而EPWM2没有发波或发波延迟很长时间，当我不使能EPWM2的TBPHS时EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;或者使能TBPHSEPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE,但EPwm2Regs.TBPHS.half.TBPHS = 0; EPWM1与EPMW2同相位同时发波正常，请问这是什么原因？谢谢
Uncle John1：
同问！我遇到的问题与楼主类似。我的是EPwm1的PHSEN使能后，PWM1就没有输出了；PHSEN关掉后，一切正常。不知楼主解决了没？
专家：你好，我这有一段如下发波程序：
//PWM1的配置
EALLOW;
// TB
EPwm1Regs.TBPRD = 300;
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
//CC
EPwm1Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty for EPWM1A
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
//AQ
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//DB
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A is the source for both delay.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBFED = 18; // FED = 10 TBCLKs initially
EPwm1Regs.DBRED = 18; // RED = 10 TBCLKs initially
//ET
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
//PWM2的配置
// TB
EPwm2Regs.TBPRD = 300;
EPwm2Regs.TBPHS.half.TBPHS = 75; // Set Phase register to PWM_PRD_USE_MIN/4 initially
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
//CC
EPwm2Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty EPWM2A
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
//AQ
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//DB
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWM1A is the source for both delay.
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBFED = 18; // FED = 10 TBCLKs initially
EPwm2Regs.DBRED = 18; // RED = 10 TBCLKs initially
//ET
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EDIS;
这段程序的本意是配置EPWM1与EPWM2相位相差90°，当我使能EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm2Regs.TBPHS.half.TBPHS = 75; EPWM1发波正常而EPWM2没有发波或发波延迟很长时间，当我不使能EPWM2的TBPHS时EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;或者使能TBPHSEPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE,但EPwm2Regs.TBPHS.half.TBPHS = 0; EPWM1与EPMW2同相位同时发波正常，请问这是什么原因？谢谢
user1880609：
回复 Uncle John1:
我的问题已解决，EPWM1模块本身就是主模块，你为什么要用到相位使能PHSEN,你的同步事件选择的是什么事件触发？
