TI中文支持网您好：
请教个问题，我用CPLD模拟SMBUS控制BQ78350电池的开关功能，需先发0x0b 0x2b 0x1197，然后再发0x0b 0x2b 0x0000，这样可以关闭电池放电功能。现在发送0x0b地址时，有ACK响应位。。之前再发一个字节后，等待ACK响应位，当等到响应位后，时钟直接被拉高了，（在等ACK时，我把时钟设置高阻态，等到响应位时钟开始，结果时钟被拉高）。。传第一个字节就正常，后面就不正常，每次传的字节和ACK，都是一个循环里的。时钟为什么会被拉高呢？
求高手帮忙看看，谢拉！
WRITE_DATA1 :
begin
if (sck_low)
begin
sda_link <= 1'b1;
case(state_bit)
FIRST : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= SECOND; end
SECOND : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= THIRD; end
THIRD : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= FOURTH; end
FOURTH : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= FIFTH; end
FIFTH : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= SIXSH; end
SIXSH : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= SEVENTH; end
SEVENTH : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= EIGHTH; end
EIGHTH : begin sda_r <= data1[31 – bit]; bit <= bit + 1'b1; state_bit <= NINETH; end
NINETH : begin sda_r <= 1'b1; sda_link <= 1'b0; state <= ACK1; end
default : begin end
endcase
end
else
begin
state <= state;
state_bit <= state_bit;
bit <= bit;
sda_r <= sda_r;
end
end
ACK1 : begin
if (!sda)
begin
if (bit == 6'd32)
begin
bit <= 6'd0;
state_bit <= FIRST;
state <= STOP1;
start_delay <= 9'd0;
end
else
begin
bit <= bit;
state_bit <= FIRST;
state <= WRITE_DATA1;
end
end
else
begin
start_delay <= 9'd0;
donez <= 1'b0; //SCK 高阻
state <= ACK1;
end
end
Star Xu：
您可以参考下面的文档，希望对您有帮助
www.ti.com/…/slua475.pdf
