28335操作ZONE0时易造成DSP死机，似乎是芯片BUG造成的，请专家帮忙-TI中文支持网

用28335 的外部地址线和数据线直接外接了一个16C2550芯片做串口扩展功能。将16c2550的寄存器地址映射到ZONE0区，CMD文件如下，发现如果在中断和主程序里都频繁操作ZONE0地址的寄存器时就会造成DSP死机。挂仿真器发现死机时，有时会进入伪中断PIE_RESERVED里。

如果仅在主程序里操作ZONE0或者仅在中断里操作ZONE0，不管有多频繁都不会造成死机。

下面是驱动和CMD的配置

void Class_XINTFDrv::Drv_XINTFInit(void)
{
EALLOW;
//— XINTCNF2 Register
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;   // XTIMCLK=SYSCLKOUT/1
XintfRegs.XINTCNF2.bit.CLKOFF = 1;   // XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKMODE = 0;   // XCLKOUT = XTIMCLK

// Make sure write buffer is empty before configuring buffering depth
while(XintfRegs.XINTCNF2.bit.WLEVEL != 0); // poll the WLEVEL bit
XintfRegs.XINTCNF2.bit.WRBUFF = 0; // No write buffering

//— XBANK Register
// Example: Assume Zone 7 is slow, so add additional BCYC cycles whenever
// switching from Zone 7 to another Zone. This will help avoid bus contention.
XintfRegs.XBANK.bit.BCYC = 7; // Add 7 cycles
XintfRegs.XBANK.bit.BANK = 7; // select zone 7

   // Zone 0————————————
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING0.bit.XWRLEAD = 3;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING0.bit.XRDLEAD = 3;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING0.bit.XRDTRAIL = 3;

// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;

    // Zone will sample XREADY signal
    XintfRegs.XTIMING0.bit.USEREADY = 0;
    XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
    // Size must be either:
    // 0,1 = x32 or
    // 1,1 = x16 other values are reserved
    XintfRegs.XTIMING0.bit.XSIZE = 3;

//— Zone 7 Configuration
XintfRegs.XTIMING7.bit.X2TIMING = 0; // Timing scale factor = 1
XintfRegs.XTIMING7.bit.XSIZE = 3;  // 3 means 16-bit interface
XintfRegs.XTIMING7.bit.READYMODE = 1; // XREADY is asynchronous
XintfRegs.XTIMING7.bit.USEREADY = 0; // Disable XREADY
XintfRegs.XTIMING7.bit.XRDLEAD = 1;  // Read lead time
XintfRegs.XTIMING7.bit.XRDACTIVE = 2; // Read active time
XintfRegs.XTIMING7.bit.XRDTRAIL = 0; // Read trail time
XintfRegs.XTIMING7.bit.XWRLEAD = 1;  // Write lead time
XintfRegs.XTIMING7.bit.XWRACTIVE = 2; // Write active time
XintfRegs.XTIMING7.bit.XWRTRAIL = 0; // Write trail time

EDIS;
//— Force a complete pipeline flush to ensure that the write to the last register
// configured occurs before returning. Safest thing to do is wait 8 full cycles.
InitXintf16Gpio();
asm(" RPT #6 || NOP");

}

MEMORY
{
PAGE 0: /* Program Memory */

RAML : origin = 0x008000, length = 0x004000 /* on-chip RAM block L0~L3 */

   FLASHH      : origin = 0x300000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x308000, length = 0x008000     /* on-chip FLASH */
   FLASHF      : origin = 0x310000, length = 0x008000     /* on-chip FLASH */
   FLASHE      : origin = 0x318000, length = 0x008000     /* on-chip FLASH */
   FLASHD      : origin = 0x320000, length = 0x008000     /* on-chip FLASH */
   FLASHC      : origin = 0x328000, length = 0x008000     /* on-chip FLASH */
   FLASHAB      : origin = 0x330000, length = 0x00FF80     /* on-chip FLASH */

   CSM_RSVD    : origin = 0x33FF80, length = 0x000076     /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x33FFF6, length = 0x000002     /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
   CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA. CSM password locations in FLASHA */
   OTP         : origin = 0x380400, length = 0x000400        /* on-chip OTP */
   ADC_CAL     : origin = 0x380080, length = 0x000009     /* ADC_cal function in Reserved memory */
     IQTABLES    : origin = 0x3FE000, length = 0x000b50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEB50, length = 0x00008c     /* IQ Math Tables in Boot ROM */    FPUTABLES   : origin = 0x3FEBDC, length = 0x0006A0     /* FPU Tables in Boot ROM */
   ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */          RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM */
  PAGE 1:   /* Data Memory */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML4L7       : origin = 0x00C000, length = 0x004000     /* on-chip RAM block L4,L5,L6,L7 */

ZONE0 : origin = 0x004100, length = 0x000F00 /* XINTF zone 0 – Data space exta SCI D E registers*/

   ZONE6       : origin = 0x0100000, length = 0x100000    /* XINTF zone 6 */   ZONE7      : origin = 0x0200000, length = 0x0100000    /* XINTF zone 7 – Data space extra ram 1M*16bit*/     DEV_EMU     : origin = 0x000880, length = 0x000180     /* device emulation registers */
   FLASH_REGS : origin = 0x000A80, length = 0x000060     /* FLASH registers */
   CSM         : origin = 0x000AE0, length = 0x000010     /* code security module registers */
    ADC_MIRROR : origin = 0x000B00, length = 0x000010     /* ADC Results register mirror */

   XINTF       : origin = 0x000B20, length = 0x000020     /* external interface registers */
     CPU_TIMER0 : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
   CPU_TIMER1 : origin = 0x000C08, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
   CPU_TIMER2 : origin = 0x000C10, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/

PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */

DMA : origin = 0x001000, length = 0x000200 /* DMA registers */

MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */

   ECANA       : origin = 0x006000, length = 0x000040     /* eCAN-A control and status registers */   ECANA_LAM   : origin = 0x006040, length = 0x000040     /* eCAN-A local acceptance masks */
   ECANA_MOTS : origin = 0x006080, length = 0x000040     /* eCAN-A message object time stamps */
   ECANA_MOTO : origin = 0x0060C0, length = 0x000040     /* eCAN-A object time-out registers */
   ECANA_MBOX : origin = 0x006100, length = 0x000100     /* eCAN-A mailboxes */

   ECANB       : origin = 0x006200, length = 0x000040     /* eCAN-B control and status registers */   ECANB_LAM   : origin = 0x006240, length = 0x000040     /* eCAN-B local acceptance masks */
   ECANB_MOTS : origin = 0x006280, length = 0x000040     /* eCAN-B message object time stamps */
   ECANB_MOTO : origin = 0x0062C0, length = 0x000040     /* eCAN-B object time-out registers */
   ECANB_MBOX : origin = 0x006300, length = 0x000100     /* eCAN-B mailboxes */

   EPWM1       : origin = 0x006800, length = 0x000022     /* Enhanced PWM 1 registers */
   EPWM2       : origin = 0x006840, length = 0x000022     /* Enhanced PWM 2 registers */
   EPWM3       : origin = 0x006880, length = 0x000022     /* Enhanced PWM 3 registers */
   EPWM4       : origin = 0x0068C0, length = 0x000022     /* Enhanced PWM 4 registers */
   EPWM5       : origin = 0x006900, length = 0x000022     /* Enhanced PWM 5 registers */
   EPWM6       : origin = 0x006940, length = 0x000022     /* Enhanced PWM 6 registers */

   ECAP1       : origin = 0x006A00, length = 0x000020     /* Enhanced Capture 1 registers */
   ECAP2       : origin = 0x006A20, length = 0x000020     /* Enhanced Capture 2 registers */
   ECAP3       : origin = 0x006A40, length = 0x000020     /* Enhanced Capture 3 registers */
   ECAP4       : origin = 0x006A60, length = 0x000020     /* Enhanced Capture 4 registers */           ECAP5       : origin = 0x006A80, length = 0x000020     /* Enhanced Capture 5 registers */           ECAP6       : origin = 0x006AA0, length = 0x000020     /* Enhanced Capture 6 registers */
   EQEP1       : origin = 0x006B00, length = 0x000040     /* Enhanced QEP 1 registers */
   EQEP2       : origin = 0x006B40, length = 0x000040     /* Enhanced QEP 2 registers */

   GPIOCTRL    : origin = 0x006F80, length = 0x000040     /* GPIO control registers */
   GPIODAT     : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */
   GPIOINT     : origin = 0x006FE0, length = 0x000020     /* GPIO interrupt/LPM registers */
                   SYSTEM      : origin = 0x007010, length = 0x000020     /* System control registers */
   SPIA        : origin = 0x007040, length = 0x000010     /* SPI-A registers */
   SCIA        : origin = 0x007050, length = 0x000010     /* SCI-A registers */
   XINTRUPT    : origin = 0x007070, length = 0x000010     /* external interrupt registers */

ADC : origin = 0x007100, length = 0x000020 /* ADC registers */

SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */

   SCIC        : origin = 0x007770, length = 0x000010     /* SCI-C registers */
     I2CA        : origin = 0x007900, length = 0x000040     /* I2C-A registers */
     CSM_PWL     : origin = 0x33FFF8, length = 0x000008     /* Part of FLASHA. CSM password locations. */

   PARTID      : origin = 0x380090, length = 0x000001     /* Part ID register location */
   SCID_RTHRDLL : origin = 0x004008, length = 0x000001 /*SCID RHR THR DLL registers*/
   SCID_IERDLM : origin = 0x004009, length = 0x000001 /*SCID IER DLM registers*/
   SCID_FCRISR : origin = 0x00400A, length = 0x000001 /*SCID FCR ISR registers*/
   SCID_LCR  : origin = 0x00400B, length = 0x000001 /*SCID LCR register*/
   SCID_MCR  : origin = 0x00400C, length = 0x000001 /*SCID MCR register*/
   SCID_LSR  : origin = 0x00400D, length = 0x000001 /*SCID LSR register*/
   SCID_MSR  : origin = 0x00400E, length = 0x000001 /*SCID MSR register*/
   SCID_SPR  : origin = 0x00400F, length = 0x000001 /*SCID SPR register*/
     SCIE_RTHRDLL : origin = 0x004010, length = 0x000001 /*SCIE RHR THR DLL registers*/
   SCIE_IERDLM : origin = 0x004011, length = 0x000001 /*SCIE IER DLM registers*/
   SCIE_FCRISR : origin = 0x004012, length = 0x000001 /*SCIE FCR ISR registers*/
   SCIE_LCR  : origin = 0x004013, length = 0x000001 /*SCIE LCR register*/
   SCIE_MCR  : origin = 0x004014, length = 0x000001 /*SCIE MCR register*/
   SCIE_LSR  : origin = 0x004015, length = 0x000001 /*SCIE LSR register*/
   SCIE_MSR  : origin = 0x004016, length = 0x000001 /*SCIE MSR register*/
   SCIE_SPR  : origin = 0x004017, length = 0x000001 /*SCIE SPR register*/
}

/* Allocate sections to memory blocks.*/
SECTIONS
{
   .cinit            : > FLASHAB      PAGE = 0
   .pinit            : > FLASHAB,     PAGE = 0
   .text             : > FLASHAB      PAGE = 0
   codestart         : > BEGIN       PAGE = 0

csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0

.econst : > FLASHAB PAGE = 0
.switch : > FLASHAB PAGE = 0

   IQmath            : > FLASHD      PAGE = 0                  /* Math Code */
   IQmathTables      : > IQTABLES, PAGE = 0, TYPE = NOLOAD     .SLOWDATA  : > ZONE0, PAGE = 1
   .EXTRAM         : > ZONE7,    PAGE = 1

   .reset            : > RESET,      PAGE = 0, TYPE = DSECT
   vectors           : > VECTORS     PAGE = 0, TYPE = DSECT
     .adc_cal     : load = ADC_CAL,   PAGE = 0, TYPE = NOLOAD

   .stack            : > RAMM1       PAGE = 1
   .esysmem          : > RAMM1       PAGE = 1
   .ebss             : > RAML4L7       PAGE = 1

PieVectTableFile : > PIE_VECT, PAGE = 1

/*** Peripheral Frame 0 Register Structures ***/
   DevEmuRegsFile    : > DEV_EMU,     PAGE = 1
   FlashRegsFile     : > FLASH_REGS, PAGE = 1
   CsmRegsFile       : > CSM,         PAGE = 1
   AdcMirrorFile     : > ADC_MIRROR, PAGE = 1   XintfRegsFile     : > XINTF,       PAGE = 1
   CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
   CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
   CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1    PieCtrlRegsFile   : > PIE_CTRL,    PAGE = 1       DmaRegsFile       : > DMA,         PAGE = 1

/*** Peripheral Frame 1 Register Structures ***/
   ECanaRegsFile     : > ECANA,       PAGE = 1
   ECanaLAMRegsFile : > ECANA_LAM    PAGE = 1     ECanaMboxesFile   : > ECANA_MBOX   PAGE = 1
   ECanaMOTSRegsFile : > ECANA_MOTS   PAGE = 1
   ECanaMOTORegsFile : > ECANA_MOTO   PAGE = 1
     ECanbRegsFile     : > ECANB,       PAGE = 1
   ECanbLAMRegsFile : > ECANB_LAM    PAGE = 1     ECanbMboxesFile   : > ECANB_MBOX   PAGE = 1
   ECanbMOTSRegsFile : > ECANB_MOTS   PAGE = 1
   ECanbMOTORegsFile : > ECANB_MOTO   PAGE = 1
     EPwm1RegsFile     : > EPWM1        PAGE = 1     EPwm2RegsFile     : > EPWM2        PAGE = 1     EPwm3RegsFile     : > EPWM3        PAGE = 1     EPwm4RegsFile     : > EPWM4        PAGE = 1     EPwm5RegsFile     : > EPWM5        PAGE = 1     EPwm6RegsFile     : > EPWM6        PAGE = 1
     ECap1RegsFile     : > ECAP1        PAGE = 1     ECap2RegsFile     : > ECAP2        PAGE = 1     ECap3RegsFile     : > ECAP3        PAGE = 1     ECap4RegsFile     : > ECAP4        PAGE = 1
   ECap5RegsFile     : > ECAP5        PAGE = 1     ECap6RegsFile     : > ECAP6        PAGE = 1

EQep1RegsFile : > EQEP1 PAGE = 1 EQep2RegsFile : > EQEP2 PAGE = 1

   GpioCtrlRegsFile : > GPIOCTRL     PAGE = 1
   GpioDataRegsFile : > GPIODAT      PAGE = 1
   GpioIntRegsFile   : > GPIOINT      PAGE = 1
  /*** Peripheral Frame 2 Register Structures ***/
   SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
   SpiaRegsFile      : > SPIA,        PAGE = 1
   SciaRegsFile      : > SCIA,        PAGE = 1
   XIntruptRegsFile : > XINTRUPT,    PAGE = 1
   AdcRegsFile       : > ADC,         PAGE = 1
   ScibRegsFile      : > SCIB,        PAGE = 1
   ScicRegsFile      : > SCIC,        PAGE = 1
   I2caRegsFile      : > I2CA,        PAGE = 1

/*** Peripheral Frame 3 Register Structures ***/
   McbspaRegsFile    : > MCBSPA,      PAGE = 1
   McbspbRegsFile    : > MCBSPB,      PAGE = 1
             /*** Code Security Module Register Structures ***/
   CsmPwlFile        : > CSM_PWL,     PAGE = 1

/*** Device Part ID Register Structures ***/
PartIdRegsFile : > PARTID, PAGE = 1

/*** SCID Registers defination Structures***/
   SCIDRTHRDLLRegsFile :>SCID_RTHRDLL,  PAGE = 1
   SCIDIERDLMRegsFile :>SCID_IERDLM,  PAGE = 1
   SCIDFCRISRRegsFile :>SCID_FCRISR,  PAGE = 1
   SCIDLCRRegsFile :>SCID_LCR, PAGE = 1
   SCIDMCRRegsFile :>SCID_MCR, PAGE = 1
   SCIDLSRRegsFile :>SCID_LSR, PAGE = 1
   SCIDMSRRegsFile :>SCID_MSR, PAGE = 1
   SCIDSPRRegsFile :>SCID_SPR, PAGE = 1
/*** SCIE Registers defination Structures***/

   SCIERTHRDLLRegsFile :>SCIE_RTHRDLL,  PAGE = 1
   SCIEIERDLMRegsFile :>SCIE_IERDLM,  PAGE = 1
   SCIEFCRISRRegsFile :>SCIE_FCRISR,  PAGE = 1
   SCIELCRRegsFile :>SCIE_LCR, PAGE = 1
   SCIEMCRRegsFile :>SCIE_MCR, PAGE = 1
   SCIELSRRegsFile :>SCIE_LSR, PAGE = 1
   SCIEMSRRegsFile :>SCIE_MSR, PAGE = 1
   SCIESPRRegsFile :>SCIE_SPR, PAGE = 1

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Forrest：

估计是程序什么地方没写好。请写个最简程序来测试一下看看是否有相同的问题，确认一下“DSP死机”的原因，您是指程序跑飞吗？

请试试看这样：在主程序修改“ZONE0地址的寄存器时”之前禁止全局中断，修改好之后再打开看看是否还会有这个问题。