f28335 mcbsp 用作SPI通过DMA传输问题

现在用F28335的MCBSPB用做SPI，并使用DMA传输数据，通讯接收正常，但发送一直出错，用示波器看了下，输出端口一直是半波的尖峰，并且在传输的最后一段才有正常的数据。检查了硬件没有问题，并且传输后面几个字节是有数据，就是开始传输的大部分字节都是一个个的尖峰。设置如下：是对照着实例来设置的。DMA的通道1是接收，通道2是发送。

void McBSPb_SPI_Cofig(void)
{
// McBSP-B register settings
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.

McbspbRegs.MFFINT.all=0x0; // Disable all interrupts

McbspbRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)

// McbspbRegs.SPCR1.bit.DLB = 1;
McbspbRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme, without clock delay
McbspbRegs.PCR.bit.CLKXP = 1; // CPOL = 1, CPHA = 1 rising edge no delay
McbspbRegs.PCR.bit.CLKRP = 0;
McbspbRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspbRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word

McbspbRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspbRegs.SRGR1.all= 0x0004; // Frame Width = 1 CLKG period, CLKGDV=4+1 CLKG=150/4/5=7.5MHz

McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
 McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
}

void DMA_CH1_Config(void)
{
// DMAInitialize();

DMACH1AddrConfig(DMACh1Dest, DMACh1Source);
DMACH1BurstConfig(0, 0, 0); // 1 word / burst as McBSP DMA mode
DMACH1TransferConfig(DIN_BUF_SIZE, 1, 0);
DMACH1WrapConfig(0xFFFF, 0, 0xFFFF, 0); // Disable wrap mode
DMACH1ModeConfig(DMA_MXEVTB, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE, SYNC_SRC, OVRFLOW_DISABLE, SIXTEEN_BIT, CHINT_END, CHINT_DISABLE);

}

void DMA_CH2_Config(void)
{
// DMAInitialize();

DMACH2AddrConfig(DMACh2Dest, DMACh2Source);
DMACH2BurstConfig(0, 0, 0); // 1 word / burst as McBSP DMA mode
DMACH2TransferConfig(DIN_BUF_SIZE, 0, 1);
DMACH2WrapConfig(0xFFFF, 0, 0xFFFF, 0); // Disable wrap mode
DMACH2ModeConfig(DMA_MREVTB, PERINT_ENABLE, ONESHOT_DISABLE, CONT_DISABLE, SYNC_DISABLE, SYNC_SRC, OVRFLOW_DISABLE, SIXTEEN_BIT, CHINT_END, CHINT_ENABLE);

}