Test Connetion结果如下:
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\gce049\AppData\Local\TEXASI~1\CCS\
ti6\0\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Feb 18 2015'.
The library build time was '23:56:50'.
The library package version is '5.1.641.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 38 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
Debug结果如下:
C28xx: GEL Output:ADC Calibration not complete, check if device is unlocked and recalibrate.C28xx: Flash Programmer: Warning: The configured device (TMS320F28335), does not match the detected device (). Flash Programming operations could be affected. Please consider modifying your target configuration file.
C28xx: GEL Output:ADC Calibration not complete, check if device is unlocked and recalibrate.C28xx: Flash Programmer: Device is locked or not connected. Operation cancelled.
C28xx: File Loader: Memory write failed: Unknown error
C28xx: GEL: File: E:\CCS\workspace_v6_1\CW_Demo\Debug\CW_Demo.out: Load failed.
请教这是仿真器问题?还是开发板问题?谢谢!
囧:
应该是芯片问题,你芯片烧写成功过吗?另外能否换一块板试一下?
Test Connetion结果如下:
[Start: Texas Instruments XDS100v2 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\gce049\AppData\Local\TEXASI~1\CCS\
ti6\0\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Feb 18 2015'.
The library build time was '23:56:50'.
The library package version is '5.1.641.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
—–[The log-file for the JTAG TCLK output generated from the PLL]———-
There is no hardware for programming the JTAG TCLK frequency.
—–[Measure the source and frequency of the final JTAG TCLKR input]——–
There is no hardware for measuring the JTAG TCLK frequency.
—–[Perform the standard path-length test on the JTAG IR and DR]———–
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 38 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
—–[Perform the Integrity scan-test on the JTAG IR]————————
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
—–[Perform the Integrity scan-test on the JTAG DR]————————
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End: Texas Instruments XDS100v2 USB Debug Probe_0]
Debug结果如下:
C28xx: GEL Output:ADC Calibration not complete, check if device is unlocked and recalibrate.C28xx: Flash Programmer: Warning: The configured device (TMS320F28335), does not match the detected device (). Flash Programming operations could be affected. Please consider modifying your target configuration file.
C28xx: GEL Output:ADC Calibration not complete, check if device is unlocked and recalibrate.C28xx: Flash Programmer: Device is locked or not connected. Operation cancelled.
C28xx: File Loader: Memory write failed: Unknown error
C28xx: GEL: File: E:\CCS\workspace_v6_1\CW_Demo\Debug\CW_Demo.out: Load failed.
请教这是仿真器问题?还是开发板问题?谢谢!
mangui zhang:
DEBug输出的都是GEL输出的
换一个GEL试试吧