TI中文支持网你好：
在我设计产品的发射端和接收端都用到TLK1521来进行数据的并串、串并处理。
在上电10分钟内，TLK1521工作正常，电路传输无误码。但大约10~15分钟时，TLK1521就会失去锁定，电路无法正常通信。
电路中TLK1521的TX_CLK由FPGA芯片输出供给，enable管脚被FPGA置为1。
为保证同步，我将发送端TLK1521的LOCK信号输出给TXD13端，然后经过链路到达接收端，将RXD13送给接收端的SYNC管脚；同理将接收端TLK1521的LOCK信号通过TXD14传给发送端，将RXD14送给发射端的SYNC。请问这样的同步方式可行吗，这样Deserializer的SYNC能接收到Serializer的LOCK信号吗？
想请教过一段时间TLK1521失去锁定的可能原因是什么？
还想请教怎么才能让发射端TLK1521和接收端TLK1521保持同步锁定，即怎样当一方失去锁定后，让另一方发送SYNC pattern让其重新锁定？
盼回复，万分感谢！！
Jeff Wang1：
Hi Anner,
你完成同步的工作方式不好，易出问题。数据手册有介绍两种同步的方式。参考一下：
rapid synchronizationThe serializer has the capability to send specific SYNC patterns consisting of nine ones and nine zeros,switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to theserializer signal within a deterministic time frame. The transmission of SYNC patterns is selected via the SYNCinput on the serializer. Upon receiving a valid SYNC pulse (wider than 6 clock cycles), 1024 cycles of SYNCpattern are sent.When the deserializer detects edge transitions at the serial input, it attempts to lock to the embedded clockinformation. The deserializer LOCKB output remains inactive while its clock/data recovery (CDR) locks to theincoming data or SYNC patterns present on the serial input. When the deserializer locks to the serial data, theLOCKB output goes active. When LOCKB is active, the deserializer outputs represent incoming serial data. Oneapproach is to tie the deserializer LOCKB output directly to the SYNC input of the transmitter. This assures thatenough SYNC patterns are sent to achieve deserializer lock.random lock synchronizationThe deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns.This allows the TLK1521 to operate in open-loop applications. Equally important is the deserializer’s ability tosupport hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the datastream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exactlock time cannot be predicted. The primary constraint on the random lock time is the initial phase relationbetween the incoming data and the GTX_CLK when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializercould enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitivemultitransition (RMT). This occurs when more than one low-high transition takes place per clock cycle overmultiple clock cycles. In the worst case, the deserializer could become locked to the data pattern rather thanthe clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, thecircuitry prevents the LOCKB from becoming active until the potential false-lock pattern changes. Notice thatthe RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern doesnot affect the deserializer state as long as the same data boundary happens each cycle. The deserializer doesnot go into lock until it finds a unique data boundary that consists of four consecutive start/stop bits at the sameposition.The deserializer stays in lock until it cannot detect the same data boundary (start/stop bits) for four consecutivecycles. Then the deserializer goes out of lock and hunts for the new data boundary (start/stop bits). In the eventof loss of synchronization, the LOCKB pin output goes inactive and the outputs (including RX_CLK) enter ahigh-impedance state. The user’s system should monitor the LOCKB pin in order to detect a loss ofsynchronization. Upon detection of loss of lock, sending SYNC patterns for resynchronization is desirable ifreestablishing lock within a specific time is critical. However, the deserializer can lock to random
