TI中文支持网我使用C语言编写CLA程序，编译通过，但是调试过程中发现软件调用task1时，程序会卡在Cla1ForceTask1andWait();中，而调用task8时，却没有反映？
下面是我的初始化：
//开时钟
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1; // CLA1
/* Assign user defined ISR to the PIE vector table */
EALLOW;
PieVectTable.CLA1_INT1 = &cla1_task1_isr;
PieVectTable.CLA1_INT2 = &cla1_task2_isr;
PieVectTable.CLA1_INT3 = &cla1_task3_isr;
PieVectTable.CLA1_INT4 = &cla1_task4_isr;
PieVectTable.CLA1_INT5 = &cla1_task5_isr;
PieVectTable.CLA1_INT6 = &cla1_task6_isr;
PieVectTable.CLA1_INT7 = &cla1_task7_isr;
PieVectTable.CLA1_INT8 = &cla1_task8_isr;
EDIS;
//Copy over the CLA code(if running in standalone mode from FLASH)
//memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);
//Copy over the CLA math tables(if running in standalone mode from FLASH
//and using the CLAMath Library)
//memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);
/* Compute all CLA task vectors */
EALLOW;
Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 -(Uint32)&Cla1Prog_Start);
EDIS;
// Step 3 : Mapping CLA tasks
/* All tasks are enabled and will be started by an ePWM trigger
* Map CLA program memory to the CLA and enable software breakpoints
*/
EALLOW;
Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;
Cla1Regs.MIER.all = 0x00FF;
EDIS;
/* Enable CLA interrupts at the group and subgroup levels */
PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER = (M_INT11 );
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
/* Switch the CLA program space to the CLA and enable software forcing
* Also switch over CLA data ram 0,1 and 2
* CAUTION: The RAMxCPUE bits can only be enabled by writing to the register
* and not the individual bit field. Furthermore, the status of these bitfields
* is not reflected in either the watch or register views – they always read as
* zeros. This is a known bug and the user is advised to test CPU accessibilty
* first before proceeding
*/
EALLOW;
Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE;//|CLA_RAM1CPUE
Cla1Regs.MCTL.bit.IACKE = 1;
EDIS;
//task8用于用户数据初始化
Cla1ForceTask1andWait();
// Cla1ForceTask3andWait();
// Cla1ForceTask8andWait();
CMD文件配置：
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x400
-stack 0x400
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
–undef_sym=__cla_scratchpad_end
–undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
// RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML0 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L0 */
RAML3 : origin = 0x009000, length = 0x001000 //cla Program
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHA : origin = 0x3D8000, length = 0x018000 /* on-chip FLASH */
FLASHC : origin = 0x3f4000, length = 0x003f80
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0006B0 /* on-chip RAM block M0 */
CLARAM0 : origin = 0x008800, length = 0x000400
CLARAM1 : origin = 0x008C00, length = 0x000400 //cla Data
CLARAM2 : origin = 0x008000, length = 0x000800
//RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML2 : origin = 0x00C000, length = 0x008000 /* on-chip RAM block L5 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */ FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = RAML0,
LOAD_START(_secureRamFuncs_loadstart),
LOAD_END(_secureRamFuncs_loadend),
RUN_START(_secureRamFuncs_runstart),
PAGE = 0
.scratchpad : > CLARAM0, PAGE = 1
.bss_cla : > CLARAM0, PAGE = 1
.const_cla : > CLARAM0, PAGE = 1
/*
Cla1Prog : LOAD = FLASHC,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
*/
///*
Cla1Prog : > RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
//*/
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
Cla1DataRam2 : > CLARAM2, PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM0,
PAGE = 1
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
//.ebss : > RAML2, PAGE = 1
//.esysmem : > RAML2, PAGE = 1
//PZ 20131121
.ebss : > RAML2, PAGE = 1
.esysmem : > RAML2, PAGE = 1
SciBuffer : > RAML2, PAGE = 1
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA, PAGE = 0
.switch : > FLASHA, PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
//DMARAML5 : > RAML5, PAGE = 1
//DMARAML6 : > RAML6, PAGE = 1
//DMARAML7 : > RAML7, PAGE = 1
//DMARAML8 : > RAML8, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
user4230078：
使用C语言编写CLA，编译通过，但是发现在执行Cla1Regs.MIER.all = 0x00FF;后Cla1Regs.MIRUN.bit.INT1自动置1了，并且无法跳出task1，我的初始化如下：
//开时钟 SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1; // CLA1
Cla1Regs.MCTL.bit.SOFTRESET = 1; /* Assign user defined ISR to the PIE vector table */ EALLOW; PieVectTable.CLA1_INT1 = &cla1_task1_isr; PieVectTable.CLA1_INT2 = &cla1_task2_isr; PieVectTable.CLA1_INT3 = &cla1_task3_isr; PieVectTable.CLA1_INT4 = &cla1_task4_isr; PieVectTable.CLA1_INT5 = &cla1_task5_isr; PieVectTable.CLA1_INT6 = &cla1_task6_isr; PieVectTable.CLA1_INT7 = &cla1_task7_isr; PieVectTable.CLA1_INT8 = &cla1_task8_isr; EDIS;
//Copy over the CLA code(if running in standalone mode from FLASH) //memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize); //Copy over the CLA math tables(if running in standalone mode from FLASH //and using the CLAMath Library) //memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);
/* Compute all CLA task vectors */ EALLOW; Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 -(Uint32)&Cla1Prog_Start); Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 -(Uint32)&Cla1Prog_Start); EDIS;
// Step 3 : Mapping CLA tasks /* All tasks are enabled and will be started by an ePWM trigger * Map CLA program memory to the CLA and enable software breakpoints */ EALLOW;
Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE; Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE; Cla1Regs.MIER.all = 0x00FF;// Cla1Regs.MCTL.bit.SOFTRESET = 1; EDIS;
/* Enable CLA interrupts at the group and subgroup levels */ PieCtrlRegs.PIEIER11.all = 0xFFFF; IER = (M_INT11 ); EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM
/* Switch the CLA program space to the CLA and enable software forcing * Also switch over CLA data ram 0,1 and 2 * CAUTION: The RAMxCPUE bits can only be enabled by writing to the register * and not the individual bit field. Furthermore, the status of these bitfields * is not reflected in either the watch or register views – they always read as * zeros. This is a known bug and the user is advised to test CPU accessibilty * first before proceeding */ EALLOW; Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE;//|CLA_RAM1CPUE Cla1Regs.MCTL.bit.IACKE = 1; EDIS; //task8用于用户数据初始化 Cla1ForceTask1andWait();
非常感谢！！！
我使用C语言编写CLA程序，编译通过，但是调试过程中发现软件调用task1时，程序会卡在Cla1ForceTask1andWait();中，而调用task8时，却没有反映？
下面是我的初始化：
//开时钟
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1; // CLA1
/* Assign user defined ISR to the PIE vector table */
EALLOW;
PieVectTable.CLA1_INT1 = &cla1_task1_isr;
PieVectTable.CLA1_INT2 = &cla1_task2_isr;
PieVectTable.CLA1_INT3 = &cla1_task3_isr;
PieVectTable.CLA1_INT4 = &cla1_task4_isr;
PieVectTable.CLA1_INT5 = &cla1_task5_isr;
PieVectTable.CLA1_INT6 = &cla1_task6_isr;
PieVectTable.CLA1_INT7 = &cla1_task7_isr;
PieVectTable.CLA1_INT8 = &cla1_task8_isr;
EDIS;
//Copy over the CLA code(if running in standalone mode from FLASH)
//memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart, (Uint32)&Cla1funcsLoadSize);
//Copy over the CLA math tables(if running in standalone mode from FLASH
//and using the CLAMath Library)
//memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart, (Uint32)&Cla1mathTablesLoadSize);
/* Compute all CLA task vectors */
EALLOW;
Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT2 = (Uint16)((Uint32)&Cla1Task2 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT3 = (Uint16)((Uint32)&Cla1Task3 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT4 = (Uint16)((Uint32)&Cla1Task4 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT5 = (Uint16)((Uint32)&Cla1Task5 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT6 = (Uint16)((Uint32)&Cla1Task6 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT7 = (Uint16)((Uint32)&Cla1Task7 -(Uint32)&Cla1Prog_Start);
Cla1Regs.MVECT8 = (Uint16)((Uint32)&Cla1Task8 -(Uint32)&Cla1Prog_Start);
EDIS;
// Step 3 : Mapping CLA tasks
/* All tasks are enabled and will be started by an ePWM trigger
* Map CLA program memory to the CLA and enable software breakpoints
*/
EALLOW;
Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = CLA_INT2_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = CLA_INT3_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = CLA_INT4_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = CLA_INT5_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = CLA_INT6_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = CLA_INT7_NONE;
Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;
Cla1Regs.MIER.all = 0x00FF;
EDIS;
/* Enable CLA interrupts at the group and subgroup levels */
PieCtrlRegs.PIEIER11.all = 0xFFFF;
IER = (M_INT11 );
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
/* Switch the CLA program space to the CLA and enable software forcing
* Also switch over CLA data ram 0,1 and 2
* CAUTION: The RAMxCPUE bits can only be enabled by writing to the register
* and not the individual bit field. Furthermore, the status of these bitfields
* is not reflected in either the watch or register views – they always read as
* zeros. This is a known bug and the user is advised to test CPU accessibilty
* first before proceeding
*/
EALLOW;
Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|CLARAM2_ENABLE;//|CLA_RAM1CPUE
Cla1Regs.MCTL.bit.IACKE = 1;
EDIS;
//task8用于用户数据初始化
Cla1ForceTask1andWait();
// Cla1ForceTask3andWait();
// Cla1ForceTask8andWait();
CMD文件配置：
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x400
-stack 0x400
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
–undef_sym=__cla_scratchpad_end
–undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
// RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
RAML0 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L0 */
RAML3 : origin = 0x009000, length = 0x001000 //cla Program
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHA : origin = 0x3D8000, length = 0x018000 /* on-chip FLASH */
FLASHC : origin = 0x3f4000, length = 0x003f80
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0006B0 /* on-chip RAM block M0 */
CLARAM0 : origin = 0x008800, length = 0x000400
CLARAM1 : origin = 0x008C00, length = 0x000400 //cla Data
CLARAM2 : origin = 0x008000, length = 0x000800
//RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML2 : origin = 0x00C000, length = 0x008000 /* on-chip RAM block L5 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */ FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = RAML0,
LOAD_START(_secureRamFuncs_loadstart),
LOAD_END(_secureRamFuncs_loadend),
RUN_START(_secureRamFuncs_runstart),
PAGE = 0
.scratchpad : > CLARAM0, PAGE = 1
.bss_cla : > CLARAM0, PAGE = 1
.const_cla : > CLARAM0, PAGE = 1
/*
Cla1Prog : LOAD = FLASHC,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
*/
///*
Cla1Prog : > RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
//*/
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
Cla1DataRam2 : > CLARAM2, PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM0,
PAGE = 1
csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
//.ebss : > RAML2, PAGE = 1
//.esysmem : > RAML2, PAGE = 1
//PZ 20131121
.ebss : > RAML2, PAGE = 1
.esysmem : > RAML2, PAGE = 1
SciBuffer : > RAML2, PAGE = 1
/* Initalized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA, PAGE = 0
.switch : > FLASHA, PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
//DMARAML5 : > RAML5, PAGE = 1
//DMARAML6 : > RAML6, PAGE = 1
//DMARAML7 : > RAML7, PAGE = 1
//DMARAML8 : > RAML8, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}
Susan Yang：您是单独调用的task8还是有其它task在运行？
您可以先看一下
e2e.ti.com/…/656855
程序会卡在Cla1ForceTask1andWait();中，是CPU在等着CLA执行完。您现在task1是什么功能？
