C6748 缓存问题

       TI 工程师提示：

       http://www.ti.com/product/TMS320C6748/technicaldocuments关于TMS320C674x DSP Cache User's Guide (Rev. A)

       上面文档中的CSLr是可以使用的，请下载下面SDK包，安装后在路径：C:\c6748_sdk\pdk_C6748_2_0_0_0\biospsp_03_00_01_00\cslr下面

       http://software-dl.ti.com/dsps/dsps_public_sw/c6000/web/bios_c6sdk/latest/index_FDS.html

       我安装上面地址下载一份后，翻开例程如下：

#include <xdc/std.h>
#include <ti/sysbios/family/c64p/Cache.h>
#include "cslr/cslr_cache.h"
#include <cslr/soc_C6748.h>
#include <stdio.h>

void config_cache(void);
int test_config(void);
int testResult=0; // Test status

int main(void)
{
// Configure the cache using register layer
config_cache();

// Verify configuration using the Cache module api's
return(test_config());
}

void config_cache(void)
{
CSL_CacheRegsOvly cacheRegs = (CSL_CacheRegsOvly)CSL_CACHE_0_REGS;
volatile unsigned int stall;

// The below writes to the CFG registers are followed by a dummy read. Mode
// switches require that a read is performed immediately after the write. The
// read stalls the cpu to ensure the mode change completes.

// Set L1P size to 32K
CSL_FINST(cacheRegs->L1PCFG,CACHE_L1PCFG_MODE,32K);
stall = cacheRegs->L1PCFG;

// Set L1D size to 32K
CSL_FINST(cacheRegs->L1DCFG,CACHE_L1DCFG_MODE,32K);
stall = cacheRegs->L1DCFG;

// Set L2 size to 64k and normal opperation
cacheRegs->L2CFG = CSL_FMKT(CACHE_L2CFG_MODE,64K)
| CSL_FMKT(CACHE_L2CFG_L2CC,NORMAL);
stall = cacheRegs->L2CFG;

// The MAR registers set the cachability of memory spaces external to the
// megamodule. Below is an example of turning on cachability for two ranges.
// Reference spru871H for a complete list the MAR ranges.

// Set MAR[192] range 0xC0000000-0xC0FFFFFF as cacheable
CSL_FINST(cacheRegs->MAR[192],CACHE_MAR_PC,CACHEABLE);

}

int test_config(void)
{
Cache_Size checkSize;
Cache_Mode checkMode;
Cache_Mar checkMar192;
Ptr baseMar192;

baseMar192 = (Ptr)0xC0000000; // MAR192 base address

// The Cache module read API's are used to verify the previous configuration
// that was performed using the register layer.

// Read L1P, L1D, and L2 cache size settings
Cache_getSize(&checkSize);

// Read L2 mode setting
checkMode = Cache_getMode(Cache_Type_L2);

// Read MAR192 setting
checkMar192 = Cache_getMar(baseMar192);

printf("\nTest cache configuraton\n");

// Verify cache size settings for L1P, L1D, and L2
if((checkSize.l1pSize==Cache_L1Size_32K)&&(checkSize.l1dSize==Cache_L1Size_32K)&&
(checkSize.l2Size==Cache_L2Size_64K))
{
printf("\nL1P size = 32K\n");
printf("L1D size = 32K\n");
printf("L2 size = 64K\n");
}
else
{
printf("\nError setting cache sizes\n");
testResult=1;
}

// Verify mode setting for L2
if(checkMode==Cache_Mode_NORMAL)
printf("\nL2 mode set to NORMAL\n");
else
{
printf("\nError setting mode\n");
testResult=1;
}

// Verify MAR192 settings
if(checkMar192==Cache_Mar_ENABLE)
printf("\nMAR192 range set to cacheable\n");
else
{
printf("\nError setting MAR range\n");
testResult=1;
}

// Display test status
if(testResult==0)
printf("\nCache configuration test: PASSED\n");
else
printf("\nCache configuration test: FAILED\n");

return(testResult);
}

       但是在文件里面  CACHE_L1PCFG_MODE  Cache_getSize()  Cache_getMode()这些函数及变量都找不到。

       我在startware的安装目录下看到了另一个版本的cache操作函数，但论坛里面好多翻译有问题。

       麻烦TI的工程师帮忙解决C6748 缓存这块的问题，论坛里面好多关于C6748 cache 都被凉到一边了。

       最好能给个验证OK的示例程序！

noaming：

CACHE_L1PCFG_MODE这个宏定义在\c6748_sdk\pdk_C6748_2_0_0_0\biospsp_03_00_01_00\cslr路径下的

cslr_cache.h中，你可以查看一下