c6455 jtag问题

我用jtag调试c6455，出现错误提示：

(Error -233 @ 0x0)
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.即jtag不能读取dsp的数据寄存器和指令寄存器。我看了一下时钟电源复位都正常，连接器也没有问题，但是我把dsp的管脚RSV32 RSV34画错了，按照datasheet这两个引脚应该上拉到1.8v，而我下拉了，其余的电路都没有问题，请问这个错误会影响JTAG吗？

注：一开始不论JTAG还是程序运行都好好的，但是某天突然就jtag连不上了，换了好几片dsp芯片，仍然提示这个错误，请问大家遇见过这种问题吗

Shine：

量一下JTAG口的各个信号是否是好的？仿真器和CCS能连其他板子吧？点击ccs里的test connection能连吗？

Shine：

回复 Shine:

正好看到这个帖子，看是否有相同的情况。http://www.deyisupport.com/question_answer/dsp_arm/c6000_dsp/f/32/p/117271/322655.aspx#322655 

zhubaojun：

回复 Shine:

仿真器没有问题，试了其他板子都没有问题，并且换了好几个仿真器都是这种提示：

test时候也会出现错误：

[Start: Spectrum Digital XDS560V2 STM USB Emulator_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

—–[Print the board config pathname(s)]————————————

C:\Users\asus\AppData\Local\Texas Instruments\ CCS\ti\0\0\BrdDat\testBoard.dat

—–[Print the reset-command software log-file]—————————–

This utility has selected a 560/2xx-class product.This utility will load the program 'sd560v2u.out'.Loaded FPGA Image: D:\ti\ccsv6\ccs_base\common\uscif\dtc_top.jbcThe library build date was 'Apr 7 2016'.The library build time was '23:42:45'.The library package version is '6.0.222.0'.The library component version is '35.35.0.0'.The controller does not use a programmable FPGA.The controller has a version number of '6' (0x00000006).The controller has an insertion length of '0' (0x00000000).The cable+pod has a version number of '8' (0x00000008).The cable+pod has a capability number of '7423' (0x00001cff).This utility will attempt to reset the controller.This utility has successfully reset the controller.

—–[Print the reset-command hardware log-file]—————————–

The scan-path will be reset by toggling the JTAG TRST signal.The controller is the Nano-TBC VHDL.The link is a 560-class second-generation-560 cable.The software is configured for Nano-TBC VHDL features.The controller will be software reset via its registers.The controller has a logic ONE on its EMU[0] input pin.The controller has a logic ONE on its EMU[1] input pin.The controller will use falling-edge timing on output pins.The controller cannot control the timing on input pins.The scan-path link-delay has been set to exactly '2' (0x0002).The utility logic has not previously detected a power-loss.The utility logic is not currently detecting a power-loss.Loaded FPGA Image: D:\ti\ccsv6\ccs_base\common\uscif\dtc_top.jbc

An error occurred while hard opening the controller.

—–[An error has occurred and this utility has aborted]——————–

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.An attempt to scan the JTAG scan-path has failed.The target's JTAG scan-path appears to be brokenwith a stuck-at-ones or stuck-at-zero fault.

[End: Spectrum Digital XDS560V2 STM USB Emulator_0]

Shine：

回复 zhubaojun:

量过JTAG信号吗？