McBSP I2S

  我用PFGA通过I2S发送数据，DSP通过McBSP接收，但总是接收不到正确的数据，可能是哪些原因呢？下面是我McBSP的配置

void init_mcbsp()
{
McbspReg->SPCR |= (1 << 24|1 << 25);
McbspReg->SPCR &= ~( 1 << 23 | // frame-sych is reset
1 << 22 | // Sample-rate generator is reset
1 << 16 | //serial port transmitter is disable
1 << 0 ); // serial port receiver is disable

McbspReg->PCR = ( 1 << 11 | // Transmit frame-sych signal is generated internally by the sample-rate generator.
0 << 10 | //Receive Frame-synchronization signal is derived from an external source. FSR is an input pin.
1 << 9 | // Transmit clock is generated internally by the sample-rate generator.
0 << 8 | //CLKR is an input pin and is driven by an external clock.
0 << 7 | // internal clock (SCLKME = 0,CLKSM = 0,CLKS)
0 << 2 | // Receive frame-sych pulse is active high
0 << 0 );// Receive data sample on falling edge of CLKR

McbspReg->SRGR = (0 << 31 | // sample rate generator clock is free running
0 << 30 | // Rising edge of CLKS generates CLKG and FSG.
0 << 29 | // sample-rate generator clock taken from CLKS (SCLKME = 0,CLKSM = 0,CLKS)
1 << 28 | //Transmit frame-sync signal (FSX) is driven by the sample-rate generator frame-sync signal (FSG).
63<< 16 | // Frame period value +1, 2 phase * 32 bit.
31 << 8 | // Frame width value +1, 0.09765625
7<< 0 ); // CLKGDV,sample rate generator clock frequency: CLKS = 25MHz, so bit clock=3.125MHz

McbspReg->RCR = ( 1 << 31 | // Dual-phase frame
0 << 24 | // 1 word in phase 2
5 << 21 | // Receive word length is 32 bits in phase 2
// 1 << 18 | // ignore first pulse
0 << 16 | // 0-bit data delay
0 << 8 | // 1 word in phase 1
5 << 5 );// Receive word length is 32 bits in phase 1

McbspReg->SPCR |= ( 1 << 23 | //frame-sych is out of reset
1 << 22 | //sample-rate generator out of reset
1 << 16 | //Serial port transmitter is enabled.
1 << 0); // serial port receiver is enable

Shine：

请问用的是哪款器件？可以先用DLB模式测一下回环有没有问题。

xincheng nalan：

回复 Shine:

用的C6748，我是这样设计的，DSP产生发送位同步和帧同步给FPGA，FPGA再将此时钟原样送给DSP作为接收位时钟和帧同步。这样设计有问题吗

Tony Tang：

xincheng nalan但总是接收不到正确的数据，可能是哪些原因呢？

数据不正确的表现是什么？错位了？

除了数据不对之外，中断之类的表现正常吗？

xincheng nalan：

回复 Tony Tang:

中断正常。发送的全都是零，接收的的不是零，完全没有规律的数字，我后来用环路测试了一下，自发自收，是可以接收到正确数据的，但是从FPGA就接收不到正确的数据

Tony Tang：

回复 xincheng nalan:

#1. 检查一下C6748的PINMUX配置。

#2. 如果#1没问题，看板子上没有有测试点，看信号线上是否有数据输出。

#3. 否则就要看FPGA的逻辑是否有问题了。