pll初始化是否正确怎么判断？

#include <stdio.h>

/*

* hello.c

*/

#include<ti/csl/csl_bootcfg.h>

#include<ti/csl/csl_bootcfgAux.h>

#include<ti/csl/csl.h>

#include<ti/csl/csl_error.h>

#include<ti/csl/csl_chip.h>

#include<ti/csl/soc.h>

#include<ti/csl/tistdtypes.h>

#include<ti/csl/csl_pllc.h>

#include<ti/csl/csl_pllcAux.h>

void Delay(myDelay,myforNum)

{

int Timer = 0;

int Num = 0;

for(Timer=0; Timer<myDelay; Timer++)

{

for(Num=0; Num<myforNum; Num++)

{;}

}

}

void main(void)

{

//CSL_sysInit(void);

printf("Main PLL Setup …\n");

//Unlock the kicker to ensure Boot configuration

//MMR is writable

CSL_BootCfgUnlockKicker();

int DUNM = 0;

if(DUNM == 0)

{

int TEMP;

Delay(100,100);

//This API opens the PLLC instance

CSL_PllcHandle hnd;

hnd = CSL_PLLC_open(0);

//read from the second control register

Uint8 pllSecCtrlVal;

pllSecCtrlVal = CSL_PLLC_getPllSecCtrlReg (hnd);

//here uint8 from 23 bit to 16 bit faulted is 0 0001 001

printf("%d\n",pllSecCtrlVal);

TEMP = pllSecCtrlVal & 0x80;

Uint32  corePLLConfig0;//mainpllctl0

Uint32  corePLLConfig1;//mainpllctl1

CSL_BootCfgGetCOREPLLConfiguration (&corePLLConfig0, &corePLLConfig1);

printf("%d\n",corePLLConfig0);

printf("%d\n",corePLLConfig1);

if (TEMP != 0)

{

printf("Pll in Bypass …\n");

//in mainpllctl1 write ENSAT = 1

corePLLConfig1 = corePLLConfig1 | 0x0040;

CSL_BootCfgSetCOREPLLConfiguration (corePLLConfig0, corePLLConfig1);

//clear PLLENSRC

//Writes to PLLEN bit take effect on PLLC only when PLLENSRC bit is set to 0.

CSL_PLLC_setPllCtrlPllEnSrc(hnd, 0);

//put PLLC in bypass mode

CSL_PLLC_setPllCtrlPllEn(hnd, 0);

// Wait for 4 RefClks

Delay(10,4);

//set bypass

pllSecCtrlVal = pllSecCtrlVal | 0x80;

CSL_PLLC_setPllSecCtrlReg (hnd, pllSecCtrlVal);

// Power down the bit 2

CSL_PLLC_setPllCtrlPllPowerDown(hnd,1);

/* Stay in a loop such that the bit is set for 5 microseconds(minimum) and  *

* then clear the bit.                                                      */

Delay(5,5);

/* Power up the PLL */

CSL_PLLC_setPllCtrlPllPowerDown(hnd,0);

}

//Put PLLC in reset

CSL_PLLC_setPllCtrlPllReset(hnd, 1);

Delay(50,100);

// Do PLLC configuration

CSL_PLLC_setPllMultiplierCtrlReg(hnd,39);

/* Set the PLL Multiplier, Divider, BWADJ                                    *

* The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register  *

* inside the PLL Controller and the PLLM[12:6] bits are controlled by the   *

* chip-level MAINPLLCTL0 Register.                                          *

* PLL Control Register (PLLM)  Layout                                       *

* |31…6   |5…0        |                                                 *

* |Reserved |PLLM         |                                                 *

*                                                                           *

* Main PLL Control Register (MAINPLLCTL0)                                   *

* |31…24   |23…19   |18…12    | 11…6   |5…0 |                     *

* |BWADJ[7:0]| Reserved |PLLM[12:6] | Reserved | PLLD |                     */

/* Set pll multipler (13 bit field) */

Uint32 num;

num = ((39 + 1) >> 1) – 1;//set MPPL's BWADJ

corePLLConfig0 &= ~(0x0ff000000);

corePLLConfig0 |= ((num << 24) & 0xFF000000);

corePLLConfig1 &= ~(0x0000000F);

corePLLConfig1 |= ((num >> 8) & 0x0000000f);

//set the pll divider

//corePLLConfig0 &= ~(0x0000003f);

//corePLLConfig0 |= (0x01 & 0x0000003f);

CSL_PLLC_setPllPreDivReg (hnd, 1, 1);

CSL_PLLC_setPllPostDivReg (hnd, 1, 1);

CSL_BootCfgSetCOREPLLConfiguration (corePLLConfig0, corePLLConfig1);

//set plldiv

Uint8 goStatus;

/*Ensure no Go operation in progress already

*CSL_PLLC_getPllDivReg()*/

CSL_PLLC_getPllStatusReg(hnd,&goStatus);

while(goStatus != 0)

{

Delay(1,1);

CSL_PLLC_getPllStatusReg(hnd,&goStatus);

}

CSL_PLLC_setPllDivReg(hnd,2,1,2);

CSL_PLLC_setPllDivReg(hnd,5,1,4);

CSL_PLLC_setPllDivReg(hnd,8,1,63);

//Set the respective ALNn bit in ALNCTL register

Uint32          alnCtlVal;

alnCtlVal   =   CSL_PLLC_getPllAlignCtrlReg (hnd);

printf("%d\n",alnCtlVal);

CSL_PLLC_setPllAlignCtrlReg(hnd,0x0ff);

alnCtlVal   =   CSL_PLLC_getPllAlignCtrlReg (hnd);

printf("%d\n",alnCtlVal);

// Start GO operation

CSL_PLLC_setPllCmdReg (hnd, 1);

//Ensure GO operation completes

CSL_PLLC_getPllStatusReg(hnd,&goStatus);

while(goStatus != 0)

{

Delay(1,1);

CSL_PLLC_getPllStatusReg(hnd,&goStatus);

}

/* Wait for the PLL Reset duration time (min: 7us)*/

Delay(7,100);

//PLL reset is released

CSL_PLLC_setPllCtrlPllReset(hnd, 0);

/*

* PLL Lock Delay needs to be 500 RefClk periods * (PLLD + 1)

* i.e., Wait for at least 500 * CLKIN cycles * (PLLD + 1) (PLL lock time)

* Using 2000 25ns RefClk periods per DM

* Wait for PLL to lock min 50 micro seconds

*

* */

Delay(100,100);

// Put PLLC back in PLL mode

pllSecCtrlVal = CSL_PLLC_getPllSecCtrlReg (hnd);

pllSecCtrlVal &= 0x7f;

CSL_PLLC_setPllSecCtrlReg (hnd, pllSecCtrlVal);

//enable PLL controller to switch to PLL mode

CSL_PLLC_setPllCtrlPllEn (hnd, 1);

// Get the CORE PLL Configuration

}

}

Andy Yin1：

可以通过观察PLL相关的寄存器配置，以及通过仪表测试相关的分频输出sysClk的时钟值是否与配置一样。