TI中文支持网近来发现一个和CACHE有关的无厘头bug,不知是什么原因！
情况是这样的：
近日发现一个地方莫名其妙的错误，然后找了很久找到了地方了！
*p_DONE[i]=3;
CACHE_wbInvL1d((void *)p_DONE[i],4,CACHE_WAIT);
当执行完第一句的时候的时候，*p_DONE[i]的值为3；
可是执行完第二句的时候的时候，*p_DONE[i]的值变为2……
测试了一下CACHE_getL1PSize();得到值为4，所以这应该与我的这个不冲突。
但是不知为何就会出现这种情况！
恳请TI的专家们或版上的大神们抽空帮忙解答！万分感激~~~
Allen35065：
你是通过JTAG单步调试读出的？你的p_DONE[i]具体地址在哪里？有没有其他的core或者master如EMAC，SRIO会写到这个地址？
Hu pc：
回复 Allen35065:
首先，谢谢这位专家or大神！
这个是用仿真器读出来的！应该没有其他的东西操作那个地址吧！其他核全都没运行！就只有一个核在运行！我给那两句话加了个while循环，结果发现一直单步执行都是先变为3，再变为2，一直循环着！不知什么原因会有这么奇怪的事情~
那个指针我是直接用地址给定向的！那块区域在CMD文件中的SECTIONS部分没有分配给任何的段！
请专家or大神继续指点！谢谢！
striker Qian：
Please make sure that each address member of your pointer array is 128Bytes(Cache Line Size) aligned and try again.
for example, p_DONE[0]= 0x00800000,p_DONE[1]= 0x00800080,p_DONE[2]= 0x00800100….
By the way ,what's the value of CACHE_getL1DSize() ?
Hu pc：
回复 striker Qian:
Thank you for your answer！
I said that the value of CACHE_getL1PSize() is 4. So the line size is 4, is it ?
striker Qian：
回复 Hu pc:
There are two L1 level caches(L1D & L1P) inside a single core and I want you to show the size of L1D cache configged. This one caches "data" from local L2RAM and we get the size using csl func "CACHE_getL1DSize()". However this size is irrespective with your problem unless the value returned is zero. Suppose it is 4K or more, your problem seems to be a failure to keep cache coherency. The solution is just I have metioned before. So is your problem solved?
BTW,L1D Cache Line Size is a fixed value 64Bytes together with L2 Cache Line Size 128Bytes in c66x dsp. Definition can be found in SPRUGY8(C66x DSP cache USG)
Hu pc：
回复 striker Qian:
Thank you again!
I'm sorry! It's my fault! But in fact, I try both "CACHE_getL1DSize()" and "CACHE_getL1PSize()", and they both return the same value,"4". That is the problem, so mysterious. The "4" means "4 BYTEs",does it ? So L1D will just invalidate cache in multiples of 4 bytes, won't it?
striker Qian：
回复 Hu pc:
Hi,hu,
I'm afraid you have confused the concept between L1D Cache Size and L1 Cache Line Size. By looking up definitons in SPRUGY8(C66x DSP cache USG) can you figure it out. Briefly,L1D Cache Size determines the cacheable area in your physical L1D RAM which can be 4KB,8KB,16KB or 32KB.However L1D Cache Line Size which represents the size of Cache Line in c66x device is a fixed value of 64Bytes. This size is the minimum operation element of CACHE_wbInvL1d(). Below is the description of that function in csl_cacheAux.h ,I paste it here in convenience.
" This function is used to invalidate and writeback the dirty lines of the block address. Although the block size can be specified in the number of bytes, the cache controller operates on whole cache lines. To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size."
If your problem is solved,please let me know.
