C667X开发板PCIE模块的时钟选择 (TI 5月23号杭州培训学员提问)

2013-06-04 分类：C6000™多核阅读(196)

Attached is the schematic diagram in page 17 of TMS320C6678 EVK board.

For PCIe clock input, there are two choice. When SEL = 0, the clock is come from IN2; when SEL = 1, the clock is come from IN1.

Please help to set the FPGA_ICS557_SEL signal to high or low , if it is possible.

EVM6657上的PCIe CLK可以是来自本板子的时钟芯片，也可以是来自AMC扩展口的时钟源，所以有一个时钟选择。