TI中文支持网Ti专家：
你们好！
目前我在使用6638芯片，想利用Queue设计8个Core之间通信的机制，QM1的Queue和QM2的Queue之间需要互传Host Packet descriptor，测试发现属于同一QM的Queue之间可以正常互传Host Packet Descriptor，但不同的QM间的Queue就不能完成Host Packet Descriptor的互传。
配置如下：
1）发送Queue使用QM2的8992；
2）QM2 FlowID=1 的配置为： RXFlow N Configuration RegisterA寄存器：RX_DEST_QMGR=0和RX_DEST_QNUM=652(QM1的pendQ)；
3）Host packet Descriptor中SourceTag- Lo=1(QM2的FlowID号)；
将Host packet descriptor push到queue8892，发现QM1的652不能收到descriptor，QM2的652(Queue8844)收到了descriptor。
我仔细看了sprugr9h.pdf/1.9节，好像在说这种使用情况，没看明白，请你们帮忙解释一下；另外如何解决QM1和QM2 Queue互传descriptor，希望能得到你们的建议。
Andy Yin1：
确认Global control register region中的QM0~3 base address register已按手册配置。
Rambo：
回复 Andy Yin1:
感谢Andy的回复，我核对了一下代码，已经按手册的推荐设置进行了配置，下面是截取的部分代码，不同QM之间仍然不能实现相互通信，不知道配置是否存在问题或者遗漏。
#define QM1_BASE_ADDRESS (0x34020000)#define QM2_BASE_ADDRESS (0x34030000)#define QM3_BASE_ADDRESS (0xFFFFFFFF)#define QM4_BASE_ADDRESS (0xFFFFFFFF)#define MAX_QM_NUM 2#define QMSS_CFG_PKTDMA_BASE_OFFSET (0x02000)
for(i=0; i<MAX_QM_NUM; i++) { pstGblCfgRegs = (CSL_Cppidma_global_configRegs *)((uint8 *)pstGblCfgRegs + i * QMSS_CFG_PKTDMA_BASE_OFFSET); CSL_FINS(pstGblCfgRegs->EMULATION_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN, (uint32)1); /* Priority Control Register: RX_PRIORITY, TX_PRIORITY */ CSL_FINS(pstGblCfgRegs->PRIORITY_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_TX_PRIORITY, g_stQmDmaGlobalConfig[enPktDmaType].uiTxPriority);
CSL_FINS(pstGblCfgRegs->PRIORITY_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RX_PRIORITY, g_stQmDmaGlobalConfig[enPktDmaType].uiRxPriority);
pstGblCfgRegs->QM_BASE_ADDRESS_REG[0] = QM1_BASE_ADDRESS + i * 0x20000; pstGblCfgRegs->QM_BASE_ADDRESS_REG[1] = QM2_BASE_ADDRESS + i * 0x20000; pstGblCfgRegs->QM_BASE_ADDRESS_REG[2] = QM3_BASE_ADDRESS; pstGblCfgRegs->QM_BASE_ADDRESS_REG[3] = QM4_BASE_ADDRESS; }
Andy Yin1：
回复 Rambo:
你配的是K1的，对K2，需要配置0x23a80000,0x23a90000,0x23aa0000, 0x23ab0000, 请对照k2 navigator user guide说明重配。
Rambo：
回复 Andy Yin1:
Andy，已经按照你的建议对代码做了修改，但测试发现QM0中的descriptor不能通过QM0的TxQueue\FlowID发送给QM1；
修改后的代码如下：
#define QM1_BASE_ADDRESS (0x23a80000)#define QM2_BASE_ADDRESS (0x23a90000)#define QM3_BASE_ADDRESS (0x23aa0000)#define QM4_BASE_ADDRESS (0x23ab0000)#define MAX_QM_NUM 2#define QMSS_CFG_PKTDMA_BASE_OFFSET (0x02000)
for(i=0; i<MAX_QM_NUM; i++) { pstGblCfgRegs = (CSL_Cppidma_global_configRegs *)((uint8 *)pstGblCfgRegs + i * QMSS_CFG_PKTDMA_BASE_OFFSET); CSL_FINS(pstGblCfgRegs->EMULATION_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_EMULATION_CONTROL_REG_LOOPBACK_EN, (uint32)1); /* Priority Control Register: RX_PRIORITY, TX_PRIORITY */ CSL_FINS(pstGblCfgRegs->PRIORITY_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_TX_PRIORITY, g_stQmDmaGlobalConfig[enPktDmaType].uiTxPriority);
CSL_FINS(pstGblCfgRegs->PRIORITY_CONTROL_REG, CPPIDMA_GLOBAL_CONFIG_PRIORITY_CONTROL_REG_RX_PRIORITY, g_stQmDmaGlobalConfig[enPktDmaType].uiRxPriority);
/* QMn Base Address Register:queue(0~4094) are set to QM0, queue(4096~8190) are set to QM1 */ #if 0 pstGblCfgRegs->QM_BASE_ADDRESS_REG[0] = QM1_BASE_ADDRESS + i * 0x20000; //0x23a80000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[1] = QM2_BASE_ADDRESS + i * 0x20000; //0x23a90000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[2] = QM3_BASE_ADDRESS; pstGblCfgRegs->QM_BASE_ADDRESS_REG[3] = QM4_BASE_ADDRESS; #else pstGblCfgRegs->QM_BASE_ADDRESS_REG[0] = QM1_BASE_ADDRESS; //0x23a80000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[1] = QM2_BASE_ADDRESS; //0x23a90000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[2] = QM3_BASE_ADDRESS; pstGblCfgRegs->QM_BASE_ADDRESS_REG[3] = QM4_BASE_ADDRESS; #endif }
//fill the info of flowCfg. s_stInterCoreRxFlowCfg[i].usSopOffset = 0; s_stInterCoreRxFlowCfg[i].usDestQnum = 652;(s_stInterCoreRxAttr.stQueResource.stRxQueObj.usQueId)&(0xFFF); s_stInterCoreRxFlowCfg[i].ucDestQmgr = 1;//(s_stInterCoreRxAttr.stQueResource.stRxQueObj.usQueId>>12)&(0x03); s_stInterCoreRxFlowCfg[i].bPsLocation = FALSE;//tail s_stInterCoreRxFlowCfg[i].ucDescType = QUEMGR_HOST_PACKET; s_stInterCoreRxFlowCfg[i].bErrorHandling = TRUE;//Starvation errors result in subsequent re-try of the descriptor allocation operation. s_stInterCoreRxFlowCfg[i].bPsinfoPresent = FALSE; s_stInterCoreRxFlowCfg[i].bEinfoPresent = FALSE; s_stInterCoreRxFlowCfg[i].ucDestTagLo = 0; s_stInterCoreRxFlowCfg[i].ucDestTagHi = 0; s_stInterCoreRxFlowCfg[i].ucSrcTagLo = 0; s_stInterCoreRxFlowCfg[i].ucSrcTagHi = 0; s_stInterCoreRxFlowCfg[i].ucSizeThreshEn = 0x0f;//use threshold. s_stInterCoreRxFlowCfg[i].ucDestTagLoSel = QUEMGR_PKTDMA_RXFLOW_DSTTAG_OVERWRITE_WITH_DESC_DST_TAG_LO; s_stInterCoreRxFlowCfg[i].ucDestTagHiSel = QUEMGR_PKTDMA_RXFLOW_DSTTAG_OVERWRITE_WITH_DESC_DST_TAG_HI; s_stInterCoreRxFlowCfg[i].ucSrcTagLoSel = QUEMGR_PKTDMA_RXFLOW_SRCTAG_OVERWRITE_WITH_FLOWID; s_stInterCoreRxFlowCfg[i].ucSrcTagHiSel = QUEMGR_PKTDMA_RXFLOW_SRCTAG_OVERWRITE_WITH_DESC_SRC_TAG; s_stInterCoreRxFlowCfg[i].usSizeThresh0 = INTERCORERX_MSGSIZE_THRESH; s_stInterCoreRxFlowCfg[i].usSizeThresh1 = INTERCORERX_MSGSIZE_THRESH; s_stInterCoreRxFlowCfg[i].usSizeThresh2 = INTERCORERX_MSGSIZE_THRESH; s_stInterCoreRxFlowCfg[i].ucFdq1Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq1Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq2Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq2Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq3Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq3Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq0Sz0Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq0Sz0Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq0Sz1Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq0Sz1Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq0Sz2Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq0Sz2Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF); s_stInterCoreRxFlowCfg[i].ucFdq0Sz3Qmgr = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i]>>12)&(0x03); s_stInterCoreRxFlowCfg[i].usFdq0Sz3Qnum = (s_stInterCoreRxAttr.stQueResource.usTxFdqId[i])&(0xFFF);
s_stInterCoreRxAttr.stQueResource.stQmssRxFlowObj[i].pstFlowCfg = &s_stInterCoreRxFlowCfg[i];
if (QueMgrDrv_qmssRxFlowIdOpen(&s_stInterCoreRxAttr.stQueResource.stQmssRxFlowObj[i]))//s_stInterCoreRxAttr.stQueResource.stQmssRxFlowObj { g_stInterCoreOms.uiAllocRxFlowIdFailed++; //To do:close the opened queue and flowId. return; }
其中
#if 0 pstGblCfgRegs->QM_BASE_ADDRESS_REG[0] = QM1_BASE_ADDRESS + i * 0x20000; //0x23a80000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[1] = QM2_BASE_ADDRESS + i * 0x20000; //0x23a90000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[2] = QM3_BASE_ADDRESS; pstGblCfgRegs->QM_BASE_ADDRESS_REG[3] = QM4_BASE_ADDRESS; #else pstGblCfgRegs->QM_BASE_ADDRESS_REG[0] = QM1_BASE_ADDRESS; //0x23a80000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[1] = QM2_BASE_ADDRESS; //0x23a90000 Keystone II pstGblCfgRegs->QM_BASE_ADDRESS_REG[2] = QM3_BASE_ADDRESS; pstGblCfgRegs->QM_BASE_ADDRESS_REG[3] = QM4_BASE_ADDRESS; #endif
两种方式都做了测试，我进行代码跟踪，发往结果发现：
QM0和QM1 652 QUEUE_STATUS_CONFIG_REG_A 都显示为0，没收到信息。
若将flow设置更改为 s_stInterCoreRxFlowCfg[i].ucDestQmgr = 0;//(s_stInterCoreRxAttr.stQueResource.stRxQueObj.usQueId>>12)&(0x03);
QM0的 652可以收到信息；
![[寻求解惑：使用TCi6638功耗评估表若干问题]-TI中文支持网](https://www.ti2k.com/wp-content/uploads/2020/05/DeyiSupport_C6000_Multicore_00.png-12.jpg)