TI中文支持网开发环境：windows32 CCS5.5
仿真器： WintechDigital XDS560V2 STM USB Emulator
硬件：自制C6678开发板
在新建的Target Configuration的Basic->connection选择WintechDigital XDS560V2 STM USB Emulator_0,Basic->Device选择TMS320C6678，然后在Advanced里给core0添加evmc6678l.gel，保存后点击TestConnection，然后出现如下信息：
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -F inform,logfile=yes -S pathlength -S integrity
[Result]
—–[Print the board config pathname(s)]————————————
C:\Users\asus\AppData\Local\.TI\1592892923\
0\0\BrdDat\testBoard.dat
—–[Print the reset-command software log-file]—————————–
This utility has selected a 560/2xx-class product.
This utility will load the program 'sd560v2u.out'.
Loaded FPGA Image: E:\CCS_V5\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Aug 19 2013'.
The library build time was '22:41:20'.
The library package version is '5.1.229.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
—–[Print the reset-command hardware log-file]—————————–
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: E:\CCS_V5\ccsv5\ccs_base\common\uscif\dtc_top.jbc
An error occurred while hard opening the controller.
—–[An error has occurred and this utility has aborted]——————–
This error is generated by TI's USCIF driver or utilities.
The value is '-501' (0xfffffe0b).
The title is 'SC_ERR_TEST_MEASURE'.
The explanation is:
The built-in scan-path length measurement failed.
The built-in scan-path reliability tests cannot be performed without knowledge of the scan-path length. Try specifying the scan-path lengths in the command-line options or board configuration file of this utility or debugger.
[End]
因为仿真器是刚买的，自制开发板还是第一次连接仿真器，所以硬件和仿真器驱动可能都会有问题，但C6678的上电应该是没有问题的，板子的DSP原理图是参考EVM6678的，前期检测到设置boot mode的GPIO电平有问题，但应该不影响仿真器连接吧，驱动的安装一开始是有问题的，后来卸了重装开起来是正常的，现在也没有其他仿真器或者完好的板子用来验证排除问题，想请教下通过以上的原因能不能锁定其中一种（软件驱动或硬件问题），硬件要检测那些？
Allen35065：
先看你是什么启动方式，检查SYSCLKOUT是否有稳定的时钟输出，BOOTSTATUS是否正确以确定DSP是否已经正常工作；
然后再查JTAG链路上的TCK,TIN,TOUT看是否有信号；
最后看JTAG驱动有没有问题。
user4217086：
回复 Allen35065:
Hi Allen,
1）BOOT设置见附件，FPGA控制DSP上电及复位，DSP输出复位状态信号为高电平，SYSCLKOUT输出时钟为208MHz，(DSP CORE CLK 外部输入为156.25MHz，芯片为1.25G的片子)，但是BOOTCOMPLETE始终为低电平，BOOT是否正确会影响JTAG连接吗？
2）测量JTAG链路 TCK是有时钟的，500KHz; 仿真器连接过程中，JTAG数据线有数据传输。
3）仿真器可以连接DSP6416，说明驱动应该没问题吧？
4）附件为板子的原理图。原理图中由于C333容值错误，修改为8.2pF后，-501错误没有了，但是出现-233错误；TRST管脚的下拉电阻是否需要焊接？
