TI中文支持网各位好：
如题，我目前把DSP作为从设备，程序设置为no_loopback，FPGA和SRIO之间的4个链路分别配置成1x模式、2.5Gbps，FPGA都能够从DSP端读写数据。但是一旦配置成SRIO4x模式，就会有如下错误：
[C66xx_0] SRIO test between two DSPs start……………………………………..
Enable Exception handling…
SRIO path configuration 4xLaneABCDInput port 0 next expected ackID value: 0x0
Output port 0 unacknowledged ackID: 0x0
Output port 0 next transmitted ackID value: 0x0
The output port 0 has encountered a degraded condition. The degraded port error threshold has been reached in the Port n Error Rate Threshold Register.
The output port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 16 is set.
The output port 0 is in the output error-stopped state.
The input port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 8 is set.
The input port 0 is in the input error-stopped state.
The input or output port 0 has encountered an error from which hardware was unable to recover.
Port 0 OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device.
The port 0 detected a delineation error. The port received an unaligned /SC/ or /PD/ or undefined code-group. The capture registers do not have valid information during this error detection.
The port 0 experienced a link timeout. The port did not receive an acknowledge or link-response control symbol within the specified time-out interval. The capture registers do not have valid information during this error detection.
Type of information logged: 0 (0 – packet, 1 – control symbol)
captured error bit in the Port Error Detect Register: 31
control symbol or Bytes 0 to 3 of the packet header that correspond to the error: 0x0
Bytes 4 to 7 of the packet header that corresponds to the error: 0x0
Bytes 8 to 11 of the packet header that corresponds to the error: 0x0
Bytes 12 to 15 of the packet header that corresponds to the error: 0x0
15 8b/10b deconding error have occurred
SP[0]_ERR_STAT = 0x01010102
SP[0]_ERR_DET = 0x00000004
Corrected Error Stop Condition. SP[0]_ERR_STAT = 0x01010102
求教这是什么导致的？每个链路单独不都能够正常通信么？
chen yi xue：
你好关于
serdes ports 和lanes的关系不是特别清楚想请教你一下
按照LANE和MODE的关系图
例如采用2X MDOE1时即只有PORT0，PORT1工作，我可以理解是这连个PORT被当成一条LANE么？
当我使用DIO传输的时候OUTPORTID怎么设置呢？
Wei Liao：
回复 chen yi xue:
你好：
我理解lanes是指的物理链路，ports指的是逻辑上的接口，一个port可以包含多个lanes。mode1中的2X指的应该是一个包含两个链路（A和B）的port，而这个port的dest_id就看你要连接的另一个端点器件的ID设置了。
chen yi xue：
回复 Wei Liao:
哈哈非常感谢你的回答
我理清楚了 4个port对应四条lanes，当设置成1x 1x时使用PORT 0，1
但是当配置成2x，1x,1x时 使用的Port是0 ，2,3
还有一个问题你改LOOPBACK模式时是将PORT SERDES都设置成了 LOOPBACK么
我这样改的话总是卡在了 ISPORTOK部也就是 对应PORT STAT一直为0；
xinjian he：
借贵宝地一用。。
请教楼主大侠一个问题
用2个6678开发板互联SRIO， NWIRTE和NREAD命令后，DSP内存的中的数据读写都正确。
但是在自制的项目中要求6678 和Xilinx ultrascale xcku040的SRIO互联时。调试中FPGA能接收来自DSP的NWRITE命令，并且将数据写入到RAM中。当DSP使用NREAD命令时，FPGA接收到了读指令，并且返回数据，但是绝大部分概率是DSP的内存没有更新，同时DSP提示“completion code =1”，偶尔会出现DSP的内存更新，同时DSP提示“completion code =0”。
不是哪位大侠能分析下是什么原因导致的
