TI中文支持网CCS版本：5.4、5.5
使用 Seed XDS560v2连接 C6674，测试连接时报以下错误：“
S[Start] Execute the command: %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ C:\DOCUME~1\Mecca\LOCALS~1\APPLIC~1\.TI\693494126\0\0\BrdDat\testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 560/2xx-class product. This utility will load the program 'seed560v2u.out'. Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc The library build date was 'Aug 19 2013'. The library build time was '22:41:20'. The library package version is '5.1.229.0'. The library component version is '35.34.40.0'. The controller does not use a programmable FPGA. The controller has a version number of '5' (0x00000005). The controller has an insertion length of '0' (0x00000000). The cable+pod has a version number of '8' (0x00000008). The cable+pod has a capability number of '7423' (0x00001cff). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- The scan-path will be reset by toggling the JTAG TRST signal. The controller is the Nano-TBC VHDL. The link is a 560-class second-generation-560 cable. The software is configured for Nano-TBC VHDL features. The controller will be software reset via its registers. The controller has a logic ONE on its EMU[0] input pin. The controller has a logic ONE on its EMU[1] input pin. The controller will use falling-edge timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '2' (0x0002). The utility logic has not previously detected a power-loss. The utility logic is not currently detecting a power-loss. Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc An error occurred while hard opening the controller. -----[An error has occurred and this utility has aborted]-------------------- This error is generated by TI's USCIF driver or utilities. The value is '-233' (0xffffff17). The title is 'SC_ERR_PATH_BROKEN'. The explanation is: The JTAG IR and DR scan-paths cannot circulate bits, they may be broken. An attempt to scan the JTAG scan-path has failed. The target's JTAG scan-path appears to be broken with a stuck-at-ones or stuck-at-zero fault. [End]
使用 XDS100 V2时，测试连接报下面的错误：
[Start] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ C:\DOCUME~1\Mecca\LOCALS~1\APPLIC~1\.TI\693494126\0\0\BrdDat\testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusb.dll'. The library build date was 'Aug 20 2013'. The library build time was '22:56:19'. The library package version is '5.1.232.0'. The library component version is '35.34.40.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000). -----[The log-file for the JTAG TCLK output generated from the PLL]---------- There is no hardware for programming the JTAG TCLK frequency. -----[Measure the source and frequency of the final JTAG TCLKR input]-------- There is no hardware for measuring the JTAG TCLK frequency. -----[Perform the standard path-length test on the JTAG IR and DR]----------- This path-length test uses blocks of 512 32-bit words. The test for the JTAG IR instruction path-length failed. The JTAG IR instruction scan-path is stuck-at-ones. The test for the JTAG DR bypass path-length failed. The JTAG DR bypass scan-path is stuck-at-ones. -----[Perform the Integrity scan-test on the JTAG IR]------------------------ This test will use blocks of 512 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF. The details of the first 8 errors have been provided. The utility will now report only the count of failed tests. Scan tests: 2, skipped: 0, failed: 1 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 2 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 3 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 4 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 5 Some of the values were corrupted - 83.3 percent. The JTAG IR Integrity scan-test has failed. -----[Perform the Integrity scan-test on the JTAG DR]------------------------ This test will use blocks of 512 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF. Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF. The details of the first 8 errors have been provided. The utility will now report only the count of failed tests. Scan tests: 2, skipped: 0, failed: 1 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 2 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 3 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 4 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 5 Some of the values were corrupted - 83.3 percent. The JTAG DR Integrity scan-test has failed. [End]
Mr.a.mike：
分别在CCS5.4和CCS5.5上使用 seed 560 v2和 xds 100 v2都出错了，而且多块板子都是一样的现象。
这样的错误是哪方面的错误呢？是硬件错误的可能性更高些？（CPU焊接出错？还是JTAG引脚有误？）还是C6674在CCS仿真环境下有特殊设置？或者这款CPU芯片在硬件设计时有什么特殊需要？比如和C6416相比？
Andy Yin1：
回复 Mr.a.mike:
JTAG连接不上目标板，有可能是硬件信号有问题，也有可能是软件配置不对。 请先对照C6672 data mannual SPRS708D确认板卡满足上电时序要求，并测量相应的供电电压及时钟的正确性，在上电后测试RESETSTAT pin及SYSCLKOUT的输出状态。
更多JTAG硬件设计及问题定位，下面这个WIKI网页总结了各种连接问题以及调试方法：
http://processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide
http://processors.wiki.ti.com/index.php/Debugging_JTAG_Connectivity_Problems
Zhan Xiang：
看起来你的JTAG链中有信号被直接拉到0了，导致SC_ERR_PATH_BROKEN，建议检查硬件连接，看是否有短路。
user4307294：
回复 Zhan Xiang:
您好，我在调试一块6747的电路板，电路板焊接完成后无法连接仿真器，错误为如下方式
采用的仿真器为XDS100V2（CCSV4），同样的硬件连接方式其他电路板可以使用。
谢谢！
user4307294：
回复 user4307294:
错误代码为Error 0x80000240/-1146
Fatal error during :Initialization ,OCS,有可能是DSP焊接有问题吗
Shine：
回复 user4307294:
图片显示不出来啊。
请问用的是c6747还是c6674? 这个帖子是c6674哦。如果是c6747的问题，建议到单核论坛提问。
C6000™单核
