TI中文支持网本人使用virtex 5 与dsp c6678 srio通信，fpga是从模式，一直使用的1x。现在调试4x的时候遇到问题，4x会自动变成1x通信，或者：dsp成4x，fpga也训练成4x，但是此时两者通信不了，查原因发现fpga srio ip核的 lnk_trdy_n信号不对，但lnk_rrdy_n信号正常，mode-sel正常。
希望得到高人解答。（Serial RapidIO v5.6）
Allen35065：
你需要检查fpga侧lnk_trdy_n代表的意义；
DSP侧你可以先做内部环回的测试以证明DSP 4X的配置是OK的，然后再与FPGA通信。
hao zhang6：
回复 Allen35065:
Allen Yin：谢谢你，DSP 4X的配置上没有问题的，
lnk_trdy_n—Indicates 7 consecutive error free control symbols have been receivedand 15 consecutive symbols have been sent. The core is fully trained and can nowtransmit data. （Link Transmit Ready）
lnk_trdy_n是核的输出信号，当都训练成4x时，唯独这个输出信号不对，所以dsp这边也初始化不了srio。
hao zhang6：
回复 Allen35065:
你好，能给我发一个c6678 srio 4x csl 的例子程序吗？非常感谢。
yimin dong：
zhanghao
你好，我现在也在做dsp和fpga的srio通讯测试；
我想请问一下，你那边fpga的程序是直接使用的ip核吗，dsp那边那个no loop模式的程序是否需要更改？
因为我现在初始化之后，感觉fpga和dsp并没有建立连接。
yao yao2：
楼主最后问题解决了吗？我现在遇到的问题和楼主差不多
moumou cheung：
回复 yao yao2:
该问题解决了。不知道你的出现的问题具体是什么呢？
Wei Liao：
回复 Allen35065:
Allen：
你好！这里该怎么调整DSP serdes的输出幅度呢？
hao zhang6：
回复 Wei Liao:
额我没有调整过，我的问题解决了但并不是通过调整SerDes幅值。
至于怎么调整 我想应该是调整SERDES_CFGTXn_CNTL寄存器的SWING值。
Wei Liao：
你好，谢谢回复！我现在调试66AK2H14和K7之间的SRIO，用到的IP核是SRIOgen2 v3.1，相比于SRIOv5.6有较大修改。DSP这边的程序和Keystone1的相比变化不大。我将DSP作为从端，SRIO每一个链路都能够以5Gbps的速率运行。但是我调试4x的时候，DSP这边就一直报错如下：
Enable Exception handling…SRIO path configuration 4xLaneABCD Input port 0 next expected ackID value: 0x0Output port 0 unacknowledged ackID: 0x0Output port 0 next transmitted ackID value: 0x0The output port 0 has encountered a degraded condition. The degraded port error threshold has been reached in the Port n Error Rate Threshold Register.The output port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 16 is set.The output port 0 is in the output error-stopped state.The input port 0 has encountered (and possibly recovered from) a transmission error. This bit is set when bit 8 is set.The input port 0 is in the input error-stopped state.The input or output port 0 has encountered an error from which hardware was unable to recover.Port 0 OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached device.The port 0 detected a delineation error. The port received an unaligned /SC/ or /PD/ or undefined code-group. The capture registers do not have valid information during this error detection.The port 0 experienced a link timeout. The port did not receive an acknowledge or link-response control symbol within the specified time-out interval. The capture registers do not have valid information during this error detection.Type of information logged: 0 (0 – packet, 1 – control symbol)captured error bit in the Port Error Detect Register: 31control symbol or Bytes 0 to 3 of the packet header that correspond to the error: 0x0Bytes 4 to 7 of the packet header that corresponds to the error: 0x0Bytes 8 to 11 of the packet header that corresponds to the error: 0x0Bytes 12 to 15 of the packet header that corresponds to the error: 0x015 8b/10b deconding error have occurred
SP[0]_ERR_STAT = 0x01010102SP[0]_ERR_DET = 0x00000004Corrected Error Stop Condition. SP[0]_ERR_STAT = 0x01010102Clearing Errors.DSP1 ready as slave for test
不知道你当时具体的问题是什么？是怎么解决的呢？望不吝赐教啊！
