TI中文支持网你好!我在使用6678的SRIO时，关于PLL的初始化，当我配置完SRIO_SERDES_CFGPLL后直接判断SRIO_SERDES_STS的状态会导致SRIO初始化偶尔不成功，但配置完SRIO_SERDES_CFGPLL后延时1s再判状态，就不会出现初始化不成功的现象，请问这是怎么回事？
Shine：
在SRIO手册里有说明To enable the internal PLL, the ENPLL bit of SRIO_SERDES_CFGPLL must be set. After setting this bit, it is necessary to allow 1s
for the regulator to stabilize. Thereafter, the PLL will take no longer than 200 reference clock cycles to lock to the required frequency, provided RIOCLK and RIOCLK are stable.
2.3.1.1 Enabling the PLL
www.ti.com/…/sprugw1b.pdf
