TI中文支持网想要配置TMS320C6678的SPI clock。
查到6678上有一组spi引脚，其中SPICLK引脚是AE1。
查询文档《KeyStone Architecture Serial Peripheral Interface (SPI) User Guide》在2.1 Clock中提到：
The SPI clock (***) is derived from the SPI module clock. The maximum clock bitrate supported is SPI module clock/2, as determined by the PRESCALE field in the SPIdata format register n (SPIFMTn). The *** frequency is calculated as:
*** frequency = [SPI module clock] / [SPIFMTn.PRESCALE + 1]When SPIFMTn.PRESCALE is cleared to 0, the *** frequency defaults to SPImodule clock/2.
所以要查询SPI module clock是多少，但是文档中没有提供。
查询文档《TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual》在7.5.1.1 Internal Clocks and Maximum Operating Frequencies里这样描述：
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but theDDR3 and the network coprocessor (PASS)) requires a PLL controller to manage the various clock divisions, gating,and synchronization. The Main PLL’s PLL controller has several SYSCLK outputs that are listed below, along withthe clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Notethat dividers are not programmable unless explicitly mentioned in the description below.• SYSCLK1: Full-rate clock for the CorePacs.• SYSCLK2: 1/x-rate clock for CorePac (emulation). Default rate for this will be 1/3. This is programmable from/1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.
• SYSCLK3: 1/2-rate clock used to clock the MSMC, HyperLink, CPU/2 SCR, DDR EMIF and CPU/2 EDMA.
• SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this aswell.
• SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable andthe max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turnedoff by software.H
• SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3EMIF.
• SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.
• SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default for this will be 1/64. This isprogrammable from /24 to /80.
• SYSCLK9: 1/12-rate clock for SmartReflex.
• SYSCLK10: 1/3-rate clock for SRIO only.
• SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5 and SYSCLK8 are programmable on theTMS320C6678 device.
这段文字中并没有告诉我SPICLK使用哪个SYSCLK。
查询文档《KeyStone Architecture Phase-Locked Loop (PLL) User's Guide》也没有找到SYSCLKn与各模块的对应关系。
我的问题是：
1，哪里能查到SYSCLKn与各模块的详细对应关系，以及对外输出引脚。
2，SPI module clock使用SYSCLK几？SPI module clock是否可以配置？如何配置？如果不能，那SPI module clock是多少？
枕水：
回复 Nancy Wang:
那 1/6-rate是指pll经过倍频分频之后的输出时钟再×1/6的意思吗？@Nancy Wang
