TI中文支持网我不加GEL（不做DDR初始化），可以正常连接器仿真器，但是加上GEL后，DDR3出事化不过，会导致仿真器掉了，哪位高手指点一下，不胜感激！！！
C66xx_1: GEL Output: Setup_Memory_Map…
C66xx_1: GEL Output: Setup_Memory_Map… Done.
C66xx_1: GEL Output:Connecting Target…
C66xx_1: GEL Output: DSP core #1
C66xx_1: GEL Output: C6678L GEL file Ver is 2.002C66xx_1: GEL Output: Global Default Setup…
C66xx_1: GEL Output: Setup Cache…C66xx_1: GEL Output: L1P = 32KC66xx_1: GEL Output: L1D = 32KC66xx_1: GEL Output: L2 = ALL SRAMC66xx_1: GEL Output: Setup Cache… Done.
C66xx_1: GEL Output: Global Default Setup… Done.
C66xx_1: GEL Output: Invalidate All Cache…
C66xx_1: GEL Output: Invalidate All Cache… Done.
C66xx_1: GEL Output: GEL Reset…
C66xx_1: GEL Output: GEL Reset… Done.
C66xx_0: GEL Output:Connecting Target…
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6678L GEL file Ver is 2.002C66xx_0: GEL Output: Global Default Setup…
C66xx_0: GEL Output: Setup Cache…C66xx_0: GEL Output: L1P = 32KC66xx_0: GEL Output: L1D = 32KC66xx_0: GEL Output: L2 = ALL SRAMC66xx_0: GEL Output: Setup Cache… Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup …C66xx_0: GEL Output: PLL in Bypass …C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup… Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains…C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains… Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup …C66xx_0: GEL Output: PA PLL Setup… Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup …C66xx_0: GEL Output: DDR3 PLL Setup… Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup … DoneC66xx_0: Trouble Reading Memory Block at 0x210000e4 on Page 0 of Length 0x4: (Error -1178 @ 0x210000E4) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: GEL: Error while executing OnTargetConnect(): target access failed at (*((unsigned int *) (0x21000000+0x000000E4))&=~(0x00008000)) [evmc6678l_cgs.gel:261] at ddr3_setup_auto_lvl_1333(0) [evmc6678l_cgs.gel:879] at Global_Default_Setup_Silent() [evmc6678l_cgs.gel:577] at OnTargetConnect() .
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1178 @ 0x41) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x348: (Error -1178 @ 0x80000000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840020 on Page 0 of Length 0x4: (Error -1178 @ 0x1840020) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840040 on Page 0 of Length 0x4: (Error -1178 @ 0x1840040) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840000 on Page 0 of Length 0x4: (Error -1178 @ 0x1840000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Register ControlRegisters_DNUM: (Error -1178 @ 0x50) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840020 on Page 0 of Length 0x4: (Error -1178 @ 0x1840020) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840040 on Page 0 of Length 0x4: (Error -1178 @ 0x1840040) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Memory Block at 0x1840000 on Page 0 of Length 0x4: (Error -1178 @ 0x1840000) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)C66xx_0: Trouble Reading Register ControlRegisters_DNUM: (Error -1178 @ 0x50) Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.747.0)
Shine：
那要检查一下DDR的参数配置，可以参考EVM板的GEL文件的配置。
Lingyang Niu：
回复 Shine:
配置应该没问题的，一个板子上两篇DSP，就这一片有这样的错误
Trolong_support：
回复 Lingyang Niu:
可能是DDR的问题，硬件损坏导致DD3无法完成初始化也是 有可能的，多方面排查。
