TI中文支持网工程师您好：
我最近调试一个使用IPC的程序，C6657的核0是一个TCP网络，核1是处理核。核1需要使用malloc申请大量内存空间，但是会默认将内存申请到L2SRAM中，超出了内存大小。于是注释掉了biso.heapsize行，使用HeapMem创建一个堆供核1的malloc使用，但是修改Memory.defaultHeapInstance后程序有时加载后直接出错，或者运行时也不能双核协调运行，请问可能是什么问题
cfg配置如下
var SysStd = xdc.useModule('xdc.runtime.SysStd');
var Fan = xdc.useModule('Tronlong.Driver.Fan');
System.SupportProxy = SysStd;
Program.sectMap["SystemHeap"] = "DDR3_CORE0";
Program.sectMap[".const"] = "L2SRAM";
Program.sectMap[".switch"] = "L2SRAM";
Program.sectMap[".cinit"] = "L2SRAM";
Program.sectMap[".vecs"] = "L2SRAM";
Program.sectMap[".DDR3_0"] = "DDR3_CORE0";
Program.sectMap[".DDR3_1"] = "DDR3_CORE1";
//BIOS.heapSize = 32768;
var Task = xdc.useModule('ti.sysbios.knl.Task');
var tsk0 = Task.create('&tsk0_func');
tsk0.instance.name = "tsk0";
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
Program.global.receive = Semaphore.create(1);
Program.global.process = Semaphore.create(0);
Program.global.sendimg = Semaphore.create(0);
Program.global.mutex = Semaphore.create(1);
var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
var procNameAry = MultiProc.getDeviceProcNames();
MultiProc.setConfig(Program.global.procName, procNameAry);
var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
var Notify = xdc.useModule('ti.sdo.ipc.Notify'); /* Notify */
var GateMP = xdc.useModule('ti.sdo.ipc.GateMP'); /* GateMP */
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion'); /* shared region */
var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ'); /* MessageQ */
var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
Ipc.sr0MemorySetup = true;
GateMP.RemoteCustom1Proxy = xdc.useModule('ti.sdo.ipc.gates.GateMPSupportNull');
var SHAREDMEM = 0x80000000;
var SHAREDMEMSIZE = 0x02000000;
{ base: SHAREDMEM, len: SHAREDMEMSIZE,
ownerProcId: 0,
isValid: true,
name: "DDR2_RAM",
});
Ipc.setEntryMeta({
remoteProcId: i,
setupMessageQ: true,
});
}
var SystemHeapParams = new HeapMem.Params;
SystemHeapParams.size = 16*16 *1024;
SystemHeapParams.sectionName = "SystemHeap";
Program.global.SystemHeap = HeapMem.create(SystemHeapParams);
Memory.defaultHeapInstance = Program.global.SystemHeap;
Global.networkOpenHook = '&NetOpenHook';
Global.networkCloseHook = '&NetCloseHook';
Global.networkIPAddrHook = '&NetIPAddrChange';
Ip.hostName = "TMS320C665x";
Ip.RestartIPTerm = true;
Ip.autoIp = false;
Ip.address = "192.168.1.30";
Ip.mask = "255.255.255.0";
var Logging = xdc.useModule('ti.uia.sysbios.LoggingSetup');
/* 实时分析 */
Logging.sysbiosHwiLogging = true;
Logging.sysbiosSwiLogging = true;
Logging.sysbiosHwiLoggingRuntimeControl = true;
Logging.sysbiosSwiLoggingRuntimeControl = true;
Logging.eventUploadMode = Logging.UploadMode_JTAGRUNMODE;
Task.defaultStackSize = 32768;
Task.defaultStackHeap = null;
Task.checkStackFlag = false;
{
IPC o = 0x80000000 l = 0x10000000 /* 256MB 多核通信专用内存 */
DDR3_CORE0 o = 0x90000000 l = 0x08000000 /* 128MB 核心 0 专用 DDR3 内存 */
DDR3_CORE1 o = 0x98000000 l = 0x08000000 /* 128MB 核心 1 专用 DDR3 内存 */
}
{ /* C 语言入口 */
.text:_c_int00 > MSMCSRAM START(BootMagic)
}
Shine：
请问加载的GEL文件里有没有对DDR3进行正确的初始化？
user5962447：
回复 Shine:
DDR3在GEL中的配置是这部分么？
#define DDR3_BASE_ADDRESS0x80000000
// DDR3 definitions
#define DDR_BASE_ADDR0x21000000#define DDR_MIDR(*(unsigned int*)(DDR_BASE_ADDR + 0x00000000))
#define DDR_SDCFG(*(unsigned int*)(DDR_BASE_ADDR + 0x00000008))
#define DDR_SDRFC(*(unsigned int*)(DDR_BASE_ADDR + 0x00000010))
#define DDR_SDTIM1(*(unsigned int*)(DDR_BASE_ADDR + 0x00000018))
#define DDR_SDTIM2(*(unsigned int*)(DDR_BASE_ADDR + 0x00000020))
#define DDR_SDTIM3(*(unsigned int*)(DDR_BASE_ADDR + 0x00000028))
#define DDR_PMCTL(*(unsigned int*)(DDR_BASE_ADDR + 0x00000038))
#define DDR_ZQCFG(*(unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
#define DDR_RDWR_LVL_RMP_CTRL(*(unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
#define DDR_TMPALRT(*(unsigned int*)(DDR_BASE_ADDR + 0x000000CC))
#define DDR_RDWR_LVL_CTRL(*(unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
#define DDR_DDRPHYC(*(unsigned int*)(DDR_BASE_ADDR + 0x000000E4))我也尝试了设置BIOS.heapSection="SystemHeap"（Program.sectMap["SystemHeap"] = "IPC";）,程序也不能正常运行，但加载后都能在main函数开始处停下。在core1中malloc处设置断点，运行后提示
[C66xx_0] ?sdo.ipc.Notify: line 376: assertion failure: A_internal: An internal error has occurred
xdc.runtime.Error.raise: terminating execution
core1能在断点处停下，运行malloc分配的地址在SystemHeap上。
Shine：
回复 user5962447:
这些只是DDR寄存器的定义，看一下有没有类似C:\ti\ccsv7\ccs_base\emulation\boards\evmc6657l\gel\evmc6657l.gel\ddr3_setup_auto_lvl_1333函数
user5962447：
回复 Shine:
有的，GEL中的代码如下
/*————————————————————–*/
/* ddr3_setup()*/
/* DDR3 initialization*/
/*————————————————————–*/
int flag;
ddr3_setup_auto_lvl_1333()
{int i,TEMP,startlo, stoplo,starthi, stophi;KICK0 = KICK0_UNLOCK;KICK1 = KICK1_UNLOCK;
/* Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us */Delay_milli_seconds(1);
/***************** 3.2 DDR3 PLL Configuration ************//* Done before */
/**************** 3.0 Leveling Register Configuration ********************//* Using partial automatic leveling due to errata */
/**************** 3.3 Leveling register configuration ********************/DDR3_CONFIG_REG_0 &= ~(0x007FE000);// clear ctrl_slave_ratio fieldDDR3_CONFIG_REG_0 |= 0x00200000;// set ctrl_slave_ratio to 0x100DDR3_CONFIG_REG_12 |= 0x08000000;// Set invert_clkout = 1DDR3_CONFIG_REG_0 |= 0xF;// set dll_lock_diff to 15
//From 4.2.1 Executing Partial Automatic Leveling — StartDDR3_CONFIG_REG_23 |= 0x00000200;//Set bit 9 = 1 to use forced ratio leveling for read DQS//From 4.2.1 Executing Partial Automatic Leveling — End
//Values with invertclkout = 1/**************** 3.3 Partial Automatic Leveling ********************/DATA0_WRLVL_INIT_RATIO = 0x00;DATA1_WRLVL_INIT_RATIO = 0x00;DATA2_WRLVL_INIT_RATIO = 0x00;DATA3_WRLVL_INIT_RATIO = 0x00;DATA4_WRLVL_INIT_RATIO = 0x33;DATA5_WRLVL_INIT_RATIO = 0x3A;DATA6_WRLVL_INIT_RATIO = 0x2C;DATA7_WRLVL_INIT_RATIO = 0x2C;DATA8_WRLVL_INIT_RATIO = 0x21;
DATA0_GTLVL_INIT_RATIO = 0x00;DATA1_GTLVL_INIT_RATIO = 0x00;DATA2_GTLVL_INIT_RATIO = 0x00;DATA3_GTLVL_INIT_RATIO = 0x00;DATA4_GTLVL_INIT_RATIO = 0xB7;DATA5_GTLVL_INIT_RATIO = 0xB1;DATA6_GTLVL_INIT_RATIO = 0xA4;DATA7_GTLVL_INIT_RATIO = 0xA4;DATA8_GTLVL_INIT_RATIO = 0x98;
//Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0DDR_DDRPHYC &= ~(0x00008000);DDR_DDRPHYC |= (0x00008000);DDR_DDRPHYC &= ~(0x00008000);
/***************** 3.4 Basic Controller and DRAM Configuration ************/DDR_SDRFC= 0x0000515C;// enable configuration
/* DDR_SDTIM1= 0x1557B9BD; */TEMP = 0;TEMP |= 0x09 << 25; // T_RP bit field 28:25TEMP |= 0x09 << 21; // T_RCD bit field 24:21TEMP |= 0x09 << 17; // T_WR bit field 20:17TEMP |= 0x17 << 12; // T_RAS bit field 16:12TEMP |= 0x20 << 6; // T_RC bit field 11:6TEMP |= 0x1 << 3; // T_RRD bit field 5:3TEMP |= 0x4; // T_WTR bit field 2:0DDR_SDTIM1 = TEMP;
/* DDR_SDTIM2= 0x304F7FE3; */TEMP = 0;TEMP |= 0x3 << 28; // T_XP bit field 30:28TEMP |= 0x71 << 16; // T_XSNR bit field 24:16TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6TEMP |= 0x4 << 3; // T_RTP bit field 5:3TEMP |= 0x3; // T_CKE bit field 2:0DDR_SDTIM2 = TEMP;
/*DDR_SDTIM3= 0x559F849F; */TEMP = 0;TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)TEMP |= 0x4 << 21; // T_CKESR bit field 23:21TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15TEMP |= 0x6A << 4; // T_RFC bit field 12:4TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)DDR_SDTIM3 = TEMP;
DDR_DDRPHYC= 0x0010010F;
DDR_ZQCFG= 0x70074c1f;
DDR_PMCTL= 0x0;
//DDR_SDRFC = 0x0000144F; // enable configuration
/* DDR_SDCFG= 0x63077AB3; *//* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;// last config write DRAM init occurs */TEMP = 0;TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27TEMP |= 0x2 << 24; // DDR_TERM bit field 26:24TEMP |= 0x2 << 21; // DYN_ODT bit field 22:21TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18TEMP |= 0x3 << 16; // CWL bit field 17:16TEMP |= 0x1 << 14; // NM bit field 15:14TEMP |= 0xE << 10; // CL bit field 13:10TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7TEMP |= 0x3 << 4; // IBANK bit field 6:4TEMP |= 0x0 << 3; // EBANK bit field 3:3TEMP |= 0x2; // PAGESIZE bit field 2:0DDR_SDCFG = TEMP;
//Wait 600us for HW init to completeDelay_milli_seconds(1);
DDR_SDRFC = 0x0000144F;//Refresh rate = (7.8*666MHz)
/**************** 4.2.1 Executing Partial Automatic Leveling ********************/
DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling – This ignores read DQS leveling result and uses ratio forced value
//(0x34) instead//Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.//Actual time = ~10-15 msDelay_milli_seconds(1);GEL_TextOut("\nDDR3 initialization is complete.\n");
}
Shine：
回复 user5962447:
是配置DDR3的，配置后，能正确读写DDR3吗？
user5962447：
回复 Shine:
可以的，在DDR3上申请了一段shareRegion空间，起始地址是0x80000000，长度是0x02000000，可以存放读取数据。问题就在于添加BIOS.heapsection="DDR3"会产生问题。或者创建一个堆到DDR3上，再调用Memory.defaultHeapInstance = Program.global.SystemHeap;也会产生问题。是IPC中不能有这样的更改么
user5962447：
回复 user5962447:
换了一种方式解决这个问题，所有malloc全部用Memory_alloc替换，最终运行成功
