TI中文支持网你好，请问为什么每一次写之间间隔一个周期，但是每一次EMIFA读之间间隔为20个周期左右？从CS信号高电平时间看出，上面的图为写的时序图，下面的图为读的时序图
Tony Tang：
刚好找到以前类似问题的回答，贴在这里供你参考（意思是一样的）：
1. The EDMA has to go through two SCRs and two bridges to get to the EMIFA. These bridges and SCRs add latency cycles to each command.2. For reads #1 is particularly important since each EMIFA read command must be fully serviced before another read command can start.3. For writes #1 does not have the same impact since writes are “fire and forget”. However, the bridge in front of the EMIFA breaks up 64 byte transfers into two 32 byte transfers. Therefore, the EMIFA can only write up to 32 bytes before it gets off the bus and then on the bus again to write another 32 bytes.
