TI中文支持网之前在开发板上是一个串行器工作，现在改为三个发三个收，引脚没有信号出来。
Tony Tang：
引脚没引出来肯定不能用了。软件上还是可以配置运行，但数据是无效的。
GUO LEE：
回复 Tony Tang:
引脚是引出来的，我的意思是之前在开发板上是一个串行器工作。现在在自己的板子上，需要要三个串行器发数据。
之前在开发板上软件是正常工作的。如今在自己的板子上，一个串行器也是能正常工作，配置三个串行器后，引脚就没有数据了。
Tony Tang：
回复 GUO LEE:
你得描述一下你是怎么修改的啊。几个串行器，则一次发送事件要给发送数据寄存器送几个数。
25.0.21.3.2 Transfers through the DMA PortCAUTIONTo perform internal transfers through the DMA port, clear XBUSEL/RBUSEL bitto 0 in the respective XFMT/RFMT registers. Failure to do so will result insoftware malfunction.Typically, you will access the McASP XRBUF registers through the DMA port. To access through the DMAport, simply have the CPU or DMA access the XRBUF through its DMA port location. See your devicespecificdata manual for the exact memory address. Through the DMA port, the DMA/CPU can service allthe serializers through a single address. The McASP automatically cycles through the appropriateserializers.For transmit operations through the DMA port, the DMA/CPU should write to the same XBUF DMA portaddress to service all of the active transmit serializers. In addition, the DMA/CPU should write to the XBUFfor all active transmit serializers in incremental (although not necessarily consecutive) order. For example,if serializers 0, 4, 5, and 7 are set up as active transmitters, the DMA/CPU should write to the XBUF DMAport address four times with data for serializers 0, 4, 5, and 7 upon each transmit data ready event. Thisexact servicing order must be followed so that data appears in the appropriate serializers.Similarly, for receive operations through the DMA port, the DMA/CPU should read from the same RBUFDMA port address to service all of the active receive serializers. In addition, reads from the active receiveserializers through the DMA port return data in incremental (although not necessarily consecutive) order.For example, if serializers 1, 2, 3, and 6 are set up as active receivers, the DMA/CPU should read fromthe RBUF DMA port address four times to obtain data for serializers 1, 2, 3, and 6 in this exact order,upon each receive data ready event.When transmitting, the DMA/CPU must write data to each serializer configured as "active" and "transmit"within each time slot. Failure to do so results in a buffer underrun condition (Section 25.0.21.6.2).Similarly, when receiving, data must be read from each serializer configured as "active" and "receive"within each time slot. Failure to do results in a buffer overrun condition (Section 25.0.21.6.3).To perform internal transfers through the DMA port, clear XBUSEL/RBUSEL bit to 0 in the respectiveXFMT/RFMT registers.
zhang yuexin：
回复 Tony Tang:
您好，我为这个数据下溢的问题烦恼一个月了，请您指导一下。我是配置了四个串行器，两个输入，两个输出。数据格式皆是32位的，一次发送事件给发送数据寄存器送两个数。
我应该怎么修改啊？下面是我的代码。
mcasp->regs->GBLCTL = 0; // Reset mcasp->regs->RGBLCTL = 0; // Reset RX mcasp->regs->XGBLCTL = 0; // Reset TX mcasp->regs->PWRDEMU = 1; // Free-running
// RX mcasp->regs->RMASK = 0xffffffff; // No padding used mcasp->regs->RFMT = 0 | (0x2<<16) //2延时 | (1 <<15) //先接收MSB | (0x0<<13) //pad extra bits with 0 | (0x0<<8) //pad with bite 0 value | (0xf<<4) //接收slot的长度为32位 | (0 <<3) //读取的XRBUF源于DMA，忽略外围引脚接口 | (0 <<0); //不进行向右旋转; // MSB 16bit, 2-delay, pad 0, DMA
mcasp->regs->AFSRCTL = 0 | (0x2<<7) //2个时隙TDM模式， | (1<<4) //接收帧长一个字， | (1<<1) //内部产生发送帧同步信号， | (0<<0); //AFSX的上升沿代表一个帧的开始
mcasp->regs->ACLKRCTL = 0x000000A4; // Rising INTERNAL CLK,(from tx side), 5分频,1010 0100 mcasp->regs->AHCLKRCTL = 0x00008000; // INT CLK (from tx side) 1000 0000 0000 0000 mcasp->regs->RTDM = 0x00000003; // Slots 0, 1 mcasp->regs->RINTCTL = 0x00000000; // Not used mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256 mcasp->regs->REVTCTL = 0;
// TX mcasp->regs->XMASK = 0xffffffff; // No padding used mcasp->regs->XFMT = 0 | (0x2<<16) //2延时 | (1 <<15) //先接收MSB | (0x0<<13) //pad extra bits with 0 | (0x0<<8) //pad with bite 0 value | (0xf<<4) //接收slot的长度为32位 | (0 <<3) //读取的XRBUF源于DMA，忽略外围引脚接口 | (0 <<0); //不进行向右旋转; // MSB 16bit, 2-delay, pad 0, DMA mcasp->regs->AFSXCTL = 0 | (0x2<<7) //2个时隙TDM模式， | (1<<4) //接收帧长一个字， | (1<<1) //内部产生发送帧同步信号， | (0<<0); //AFSX的上升沿代表一个帧的开始
mcasp->regs->ACLKXCTL = 0x00000064; // ASYNC, Rising INTERNAL CLK, div-by-5 0110 0100 mcasp->regs->AHCLKXCTL = 0x00008000; // INT CLK mcasp->regs->XTDM = 0x00000003; // Slots 0, 1 mcasp->regs->XINTCTL = 0x00000000; // Not used mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256 mcasp->regs->XEVTCTL = 0;
mcasp->regs->SRCTL0 = 0x000E; // MCASP0.AXR0[0] –> DIN mcasp->regs->SRCTL1 = 0x000E; // MCASP0.AXR0[1] –> DIN mcasp->regs->SRCTL2 = 0x000D; // MCASP0.AXR0[2] <– DOUT mcasp->regs->SRCTL3 = 0x000D; // MCASP0.AXR0[3] <– DOUT
mcasp->regs->PFUNC = 0; // All MCASPs mcasp->regs->PDIR = 0xB400000C; // All inputs except ACLKR0, ACLKX0, AFSR0, AFSX0, AXR[2],AXR[3]
mcasp->regs->DITCTL = 0x00000000; // Not used mcasp->regs->DLBCTL = 0x00000000; // Not used mcasp->regs->AMUTE = 0x00000000; // Not used
// Starting sections of the McASP mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
/* setup_edma_pingpong_rcv(mcasp_rcv_register, rcv_ping_L, rcv_pong_L, rcv_ping_R, rcv_pong_R, BYTES_PER_SAMPLE, SAMPLES_PER_BUF);
setup_edma_pingpong_xmt(xmt_ping_L, xmt_pong_L, xmt_ping_R, xmt_pong_R, mcasp_xmt_register, BYTES_PER_SAMPLE, SAMPLES_PER_BUF); */
// LOG_printf(&trace, ": set up EDMA fine!");
// EdmaEnableChannel(EDMA_MCASPRXCH, 0); // EdmaEnableChannel(EDMA_MCASPTXCH, 0);
// LOG_printf(&trace, ": EDMA channel enabled!");
// EdmaIntEnable(EDMA_RCV_PING_TCC); // EdmaIntEnable(EDMA_RCV_PONG_TCC); // EdmaIntEnable(EDMA_XMT_PING_TCC); // EdmaIntEnable(EDMA_XMT_PONG_TCC);
mcasp->regs->XSTAT = 0x0000ffff; // Clear all mcasp->regs->RSTAT = 0x0000ffff; // Clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
// Write a 0, so that no underrun occurs after releasing the state machine mcasp->regs->XBUF2 = 0; mcasp->regs->XBUF3 = 0; mcasp->regs->RBUF0 = 0; mcasp->regs->RBUF1 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON ); // LOG_printf(&trace, "[MCASP]: mcasp finished…");
// if(mcasp->regs->RSTAT & 00000001==1)// mcasp->regs->RSTAT = 0x0000ffff;
}
//——————————————————————————// End of File mcasp.c//——————————————————————————
